Imported Upstream version 3.2.2

[debian/gnuradio] / usrp / fpga / sdr_lib / cordic_stage.v

diff --git a/usrp/fpga/sdr_lib/cordic_stage.v b/usrp/fpga/sdr_lib/cordic_stage.v
index 0106da5cb1fc5e61bd0882bef36da1b5910dde34..d44998b0d68ad12058b143dfe5a12efa0621c5ce 100755 (executable)
--- a/usrp/fpga/sdr_lib/cordic_stage.v
+++ b/usrp/fpga/sdr_lib/cordic_stage.v
@@ -45,7 +45,7 @@ module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
          yo <= #1 0;
          zo <= #1 0;
        end
-     else //if(enable)
+     else if(enable)
        begin
          xo <= #1 z_is_pos ?   
                xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :