Remove usrp1 and usrp2 FPGA files. These are now hosted at:

[debian/gnuradio] / usrp / fpga / megacells / fifo_4kx16_dc.cmp

diff --git a/usrp/fpga/megacells/fifo_4kx16_dc.cmp b/usrp/fpga/megacells/fifo_4kx16_dc.cmp
deleted file mode 100755 (executable)
index 356de4d..0000000
--- a/usrp/fpga/megacells/fifo_4kx16_dc.cmp
+++ /dev/null
@@ -1,31 +0,0 @@
---Copyright (C) 1991-2006 Altera Corporation\r
---Your use of Altera Corporation's design tools, logic functions \r
---and other software and tools, and its AMPP partner logic \r
---functions, and any output files any of the foregoing \r
---(including device programming or simulation files), and any \r
---associated documentation or information are expressly subject \r
---to the terms and conditions of the Altera Program License \r
---Subscription Agreement, Altera MegaCore Function License \r
---Agreement, or other applicable license agreement, including, \r
---without limitation, that your use is for the sole purpose of \r
---programming logic devices manufactured by Altera and sold by \r
---Altera or its authorized distributors.  Please refer to the \r
---applicable agreement for further details.\r
-\r
-\r
-component fifo_4kx16_dc\r
-       PORT\r
-       (\r
-               aclr            : IN STD_LOGIC  := '0';\r
-               data            : IN STD_LOGIC_VECTOR (15 DOWNTO 0);\r
-               rdclk           : IN STD_LOGIC ;\r
-               rdreq           : IN STD_LOGIC ;\r
-               wrclk           : IN STD_LOGIC ;\r
-               wrreq           : IN STD_LOGIC ;\r
-               q               : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);\r
-               rdempty         : OUT STD_LOGIC ;\r
-               rdusedw         : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);\r
-               wrfull          : OUT STD_LOGIC ;\r
-               wrusedw         : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)\r
-       );\r
-end component;\r