+++ /dev/null
-// megafunction wizard: %FIFO%\r
-// GENERATION: STANDARD\r
-// VERSION: WM1.0\r
-// MODULE: dcfifo \r
-\r
-// ============================================================\r
-// File Name: fifo_4k_18.v\r
-// Megafunction Name(s):\r
-// dcfifo\r
-//\r
-// Simulation Library Files(s):\r
-// altera_mf\r
-// ============================================================\r
-// ************************************************************\r
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
-//\r
-// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition\r
-// ************************************************************\r
-\r
-\r
-//Copyright (C) 1991-2007 Altera Corporation\r
-//Your use of Altera Corporation's design tools, logic functions \r
-//and other software and tools, and its AMPP partner logic \r
-//functions, and any output files from any of the foregoing \r
-//(including device programming or simulation files), and any \r
-//associated documentation or information are expressly subject \r
-//to the terms and conditions of the Altera Program License \r
-//Subscription Agreement, Altera MegaCore Function License \r
-//Agreement, or other applicable license agreement, including, \r
-//without limitation, that your use is for the sole purpose of \r
-//programming logic devices manufactured by Altera and sold by \r
-//Altera or its authorized distributors. Please refer to the \r
-//applicable agreement for further details.\r
-\r
-\r
-// synopsys translate_off\r
-`timescale 1 ps / 1 ps\r
-// synopsys translate_on\r
-module fifo_4k_18 (\r
- aclr,\r
- data,\r
- rdclk,\r
- rdreq,\r
- wrclk,\r
- wrreq,\r
- q,\r
- rdempty,\r
- rdusedw,\r
- wrfull,\r
- wrusedw);\r
-\r
- input aclr;\r
- input [17:0] data;\r
- input rdclk;\r
- input rdreq;\r
- input wrclk;\r
- input wrreq;\r
- output [17:0] q;\r
- output rdempty;\r
- output [11:0] rdusedw;\r
- output wrfull;\r
- output [11:0] wrusedw;\r
-\r
- wire sub_wire0;\r
- wire [11:0] sub_wire1;\r
- wire sub_wire2;\r
- wire [17:0] sub_wire3;\r
- wire [11:0] sub_wire4;\r
- wire rdempty = sub_wire0;\r
- wire [11:0] wrusedw = sub_wire1[11:0];\r
- wire wrfull = sub_wire2;\r
- wire [17:0] q = sub_wire3[17:0];\r
- wire [11:0] rdusedw = sub_wire4[11:0];\r
-\r
- dcfifo dcfifo_component (\r
- .wrclk (wrclk),\r
- .rdreq (rdreq),\r
- .aclr (aclr),\r
- .rdclk (rdclk),\r
- .wrreq (wrreq),\r
- .data (data),\r
- .rdempty (sub_wire0),\r
- .wrusedw (sub_wire1),\r
- .wrfull (sub_wire2),\r
- .q (sub_wire3),\r
- .rdusedw (sub_wire4)\r
- // synopsys translate_off\r
- ,\r
- .rdfull (),\r
- .wrempty ()\r
- // synopsys translate_on\r
- );\r
- defparam\r
- dcfifo_component.add_ram_output_register = "OFF",\r
- dcfifo_component.clocks_are_synchronized = "FALSE",\r
- dcfifo_component.intended_device_family = "Cyclone",\r
- dcfifo_component.lpm_numwords = 4096,\r
- dcfifo_component.lpm_showahead = "ON",\r
- dcfifo_component.lpm_type = "dcfifo",\r
- dcfifo_component.lpm_width = 18,\r
- dcfifo_component.lpm_widthu = 12,\r
- dcfifo_component.overflow_checking = "OFF",\r
- dcfifo_component.underflow_checking = "OFF",\r
- dcfifo_component.use_eab = "ON";\r
-\r
-\r
-endmodule\r
-\r
-// ============================================================\r
-// CNX file retrieval info\r
-// ============================================================\r
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"\r
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"\r
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"\r
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"\r
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"\r
-// Retrieval info: PRIVATE: Clock NUMERIC "4"\r
-// Retrieval info: PRIVATE: Depth NUMERIC "4096"\r
-// Retrieval info: PRIVATE: Empty NUMERIC "1"\r
-// Retrieval info: PRIVATE: Full NUMERIC "1"\r
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"\r
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"\r
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"\r
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"\r
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"\r
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"\r
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"\r
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"\r
-// Retrieval info: PRIVATE: Width NUMERIC "18"\r
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"\r
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"\r
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"\r
-// Retrieval info: PRIVATE: output_width NUMERIC "18"\r
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"\r
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"\r
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"\r
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"\r
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"\r
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"\r
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"\r
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"\r
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"\r
-// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"\r
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"\r
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"\r
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"\r
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"\r
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"\r
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"\r
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"\r
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"\r
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr\r
-// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]\r
-// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]\r
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk\r
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty\r
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
-// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]\r
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk\r
-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull\r
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
-// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]\r
-// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0\r
-// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0\r
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0\r
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0\r
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0\r
-// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0\r
-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0\r
-// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0\r
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE\r
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE\r
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE\r
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE\r
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE\r
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE\r
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE\r
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE\r
-// Retrieval info: LIB_FILE: altera_mf\r
projects / debian / gnuradio / blobdiff