--- /dev/null
+// megafunction wizard: %FIFO%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: scfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_1kx16.v\r
+// Megafunction Name(s):\r
+// scfifo\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2006 Altera Corporation\r
+//Your use of Altera Corporation's design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors. Please refer to the \r
+//applicable agreement for further details.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module fifo_1kx16 (\r
+ aclr,\r
+ clock,\r
+ data,\r
+ rdreq,\r
+ wrreq,\r
+ almost_empty,\r
+ empty,\r
+ full,\r
+ q,\r
+ usedw);\r
+\r
+ input aclr;\r
+ input clock;\r
+ input [15:0] data;\r
+ input rdreq;\r
+ input wrreq;\r
+ output almost_empty;\r
+ output empty;\r
+ output full;\r
+ output [15:0] q;\r
+ output [9:0] usedw;\r
+\r
+ wire [9:0] sub_wire0;\r
+ wire sub_wire1;\r
+ wire sub_wire2;\r
+ wire [15:0] sub_wire3;\r
+ wire sub_wire4;\r
+ wire [9:0] usedw = sub_wire0[9:0];\r
+ wire empty = sub_wire1;\r
+ wire almost_empty = sub_wire2;\r
+ wire [15:0] q = sub_wire3[15:0];\r
+ wire full = sub_wire4;\r
+\r
+ scfifo scfifo_component (\r
+ .rdreq (rdreq),\r
+ .aclr (aclr),\r
+ .clock (clock),\r
+ .wrreq (wrreq),\r
+ .data (data),\r
+ .usedw (sub_wire0),\r
+ .empty (sub_wire1),\r
+ .almost_empty (sub_wire2),\r
+ .q (sub_wire3),\r
+ .full (sub_wire4)\r
+ // synopsys translate_off\r
+ ,\r
+ .sclr (),\r
+ .almost_full ()\r
+ // synopsys translate_on\r
+ );\r
+ defparam\r
+ scfifo_component.add_ram_output_register = "OFF",\r
+ scfifo_component.almost_empty_value = 504,\r
+ scfifo_component.intended_device_family = "Cyclone",\r
+ scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",\r
+ scfifo_component.lpm_numwords = 1024,\r
+ scfifo_component.lpm_showahead = "OFF",\r
+ scfifo_component.lpm_type = "scfifo",\r
+ scfifo_component.lpm_width = 16,\r
+ scfifo_component.lpm_widthu = 10,\r
+ scfifo_component.overflow_checking = "ON",\r
+ scfifo_component.underflow_checking = "ON",\r
+ scfifo_component.use_eab = "ON";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"\r
+// Retrieval info: PRIVATE: Clock NUMERIC "0"\r
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"\r
+// Retrieval info: PRIVATE: Empty NUMERIC "1"\r
+// Retrieval info: PRIVATE: Full NUMERIC "1"\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"\r
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"\r
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"\r
+// Retrieval info: PRIVATE: Width NUMERIC "16"\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"\r
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"\r
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"\r
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"\r
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr\r
+// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty\r
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]\r
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty\r
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full\r
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0\r
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0\r
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0\r
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0\r
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0\r
+// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE\r