Imported Upstream version 3.2.2

[debian/gnuradio] / usrp / fpga / megacells / fifo_1kx16.cmp

diff --git a/usrp/fpga/megacells/fifo_1kx16.cmp b/usrp/fpga/megacells/fifo_1kx16.cmp
new file mode 100755 (executable)
index 0000000..9b2c2c0
--- /dev/null
+++ b/usrp/fpga/megacells/fifo_1kx16.cmp
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2006 Altera Corporation\r
+--Your use of Altera Corporation's design tools, logic functions \r
+--and other software and tools, and its AMPP partner logic \r
+--functions, and any output files any of the foregoing \r
+--(including device programming or simulation files), and any \r
+--associated documentation or information are expressly subject \r
+--to the terms and conditions of the Altera Program License \r
+--Subscription Agreement, Altera MegaCore Function License \r
+--Agreement, or other applicable license agreement, including, \r
+--without limitation, that your use is for the sole purpose of \r
+--programming logic devices manufactured by Altera and sold by \r
+--Altera or its authorized distributors.  Please refer to the \r
+--applicable agreement for further details.\r
+\r
+\r
+component fifo_1kx16\r
+       PORT\r
+       (\r
+               aclr            : IN STD_LOGIC ;\r
+               clock           : IN STD_LOGIC ;\r
+               data            : IN STD_LOGIC_VECTOR (15 DOWNTO 0);\r
+               rdreq           : IN STD_LOGIC ;\r
+               wrreq           : IN STD_LOGIC ;\r
+               almost_empty            : OUT STD_LOGIC ;\r
+               empty           : OUT STD_LOGIC ;\r
+               full            : OUT STD_LOGIC ;\r
+               q               : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);\r
+               usedw           : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)\r
+       );\r
+end component;\r