+++ /dev/null
-//`include "../../firmware/include/fpga_regs_common.v"\r
-//`include "../../firmware/include/fpga_regs_standard.v"\r
-module rx_buffer_inband\r
- ( input usbclk,\r
- input bus_reset,\r
- input reset, // DSP side reset (used here), do not reset registers\r
- input reset_regs, //Only reset registers\r
- output [15:0] usbdata,\r
- input RD,\r
- output wire have_pkt_rdy,\r
- output reg rx_overrun,\r
- input wire [3:0] channels,\r
- input wire [15:0] ch_0,\r
- input wire [15:0] ch_1,\r
- input wire [15:0] ch_2,\r
- input wire [15:0] ch_3,\r
- input wire [15:0] ch_4,\r
- input wire [15:0] ch_5,\r
- input wire [15:0] ch_6,\r
- input wire [15:0] ch_7,\r
- input rxclk,\r
- input rxstrobe,\r
- input clear_status,\r
- input [6:0] serial_addr, \r
- input [31:0] serial_data, \r
- input serial_strobe,\r
- output wire [15:0] debugbus,\r
- \r
- //Connection with tx_inband\r
- input rx_WR,\r
- input [15:0] rx_databus,\r
- input rx_WR_done,\r
- output reg rx_WR_enabled,\r
- //signal strength\r
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,\r
- input wire [31:0] rssi_2, input wire [31:0] rssi_3,\r
- input wire [1:0] tx_underrun\r
- );\r
- \r
- parameter NUM_CHAN = 1;\r
- genvar i ;\r
- \r
- // FX2 Bug Fix\r
- reg [8:0] read_count;\r
- always @(negedge usbclk)\r
- if(bus_reset)\r
- read_count <= #1 9'd0;\r
- else if(RD & ~read_count[8])\r
- read_count <= #1 read_count + 9'd1;\r
- else\r
- read_count <= #1 RD ? read_count : 9'b0;\r
- \r
- // Time counter\r
- reg [31:0] timestamp_clock;\r
- always @(posedge rxclk)\r
- if (reset)\r
- timestamp_clock <= 0;\r
- else\r
- timestamp_clock <= timestamp_clock + 1;\r
- \r
- // USB side fifo\r
- wire [11:0] rdusedw;\r
- wire [11:0] wrusedw;\r
- wire [15:0] fifodata;\r
- wire [15:0] fifodata_il[0:NUM_CHAN];\r
- wire WR;\r
- wire have_space;\r
- reg sel;\r
- reg wr;\r
-\r
- always@(posedge rxclk)\r
- begin\r
- if(reset)\r
- begin\r
- sel<=1;\r
- wr<=0;\r
- end\r
- else if(rxstrobe)\r
- begin\r
- sel<=0;\r
- wr<=1;\r
- end\r
- else if(wr&~sel)\r
- sel<=1;\r
- else if(wr&sel)\r
- wr<=0;\r
- else\r
- wr<=0;\r
- end\r
-\r
- assign fifodata_il[0] = (sel)?ch_1:ch_0;\r
- assign fifodata_il[1] = (sel)?ch_3:ch_2;\r
-\r
- fifo_4kx16_dc rx_usb_fifo (\r
- .aclr ( reset ),\r
- .data ( fifodata ),\r
- .rdclk ( ~usbclk ),\r
- .rdreq ( RD & ~read_count[8] ),\r
- .wrclk ( rxclk ),\r
- .wrreq ( WR ),\r
- .q ( usbdata ),\r
- .rdempty ( ),\r
- .rdusedw ( rdusedw ),\r
- .wrfull ( ),\r
- .wrusedw ( wrusedw ) );\r
- \r
- assign have_pkt_rdy = (rdusedw >= 12'd256);\r
- assign have_space = (wrusedw < 12'd760);\r
- \r
- // Rx side fifos\r
- // These are of size [NUM_CHAN:0] because the extra channel is used for the\r
- // RX command channel. If there were no command channel, they would be\r
- // NUM_CHAN-1.\r
- wire chan_rdreq;\r
- wire [15:0] chan_fifodata;\r
- wire [9:0] chan_usedw;\r
- wire [NUM_CHAN:0] chan_empty;\r
- wire [3:0] rd_select;\r
- wire [NUM_CHAN:0] rx_full;\r
- \r
- packet_builder #(NUM_CHAN) rx_pkt_builer (\r
- .rxclk ( rxclk ),\r
- .reset ( reset ),\r
- .timestamp_clock ( timestamp_clock ),\r
- .channels ( NUM_CHAN ),\r
- .chan_rdreq ( chan_rdreq ),\r
- .chan_fifodata ( chan_fifodata ),\r
- .chan_empty ( chan_empty ),\r
- .rd_select ( rd_select ),\r
- .chan_usedw ( chan_usedw ),\r
- .WR ( WR ),\r
- .fifodata ( fifodata ),\r
- .have_space ( have_space ),\r
- .rssi_0(rssi_0), .rssi_1(rssi_1),\r
- .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),\r
- .underrun(tx_underrun));\r
- \r
- // Detect overrun\r
- always @(posedge rxclk)\r
- if(reset)\r
- rx_overrun <= 1'b0;\r
- else if(rx_full[0])\r
- rx_overrun <= 1'b1;\r
- else if(clear_status)\r
- rx_overrun <= 1'b0;\r
-\r
- \r
- // FIXME: what is the purpose of these two lines?\r
- wire [15:0]ch[NUM_CHAN:0];\r
- assign ch[0] = ch_0;\r
- \r
- wire cmd_empty;\r
- \r
- always @(posedge rxclk)\r
- if(reset)\r
- rx_WR_enabled <= 1;\r
- else if(cmd_empty)\r
- rx_WR_enabled <= 1;\r
- else if(rx_WR_done)\r
- rx_WR_enabled <= 0;\r
-\r
-\r
- // Of Size 0:NUM_CHAN due to extra command channel.\r
- wire [15:0] dataout [0:NUM_CHAN];\r
- wire [9:0] usedw [0:NUM_CHAN];\r
- wire empty[0:NUM_CHAN];\r
- \r
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)\r
- begin : generate_channel_fifos\r
-\r
- wire rdreq;\r
-\r
- assign rdreq = (rd_select == i) & chan_rdreq;\r
-\r
- fifo_1kx16 rx_chan_fifo (\r
- .aclr ( reset ),\r
- .clock ( rxclk ),\r
- .data ( fifodata_il[i] ),\r
- .rdreq ( rdreq ),\r
- .wrreq ( ~rx_full[i] & wr),\r
- .empty (empty[i]),\r
- .full (rx_full[i]),\r
- .q ( dataout[i]),\r
- .usedw ( usedw[i]),\r
- .almost_empty(chan_empty[i])\r
- );\r
- end\r
- endgenerate\r
- \r
- wire [7:0] debug;\r
- \r
- fifo_1kx16 rx_cmd_fifo (\r
- .aclr ( reset ),\r
- .clock ( rxclk ),\r
- .data ( rx_databus ),\r
- .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),\r
- .wrreq ( rx_WR & rx_WR_enabled),\r
- .empty ( cmd_empty),\r
- .full ( rx_full[NUM_CHAN] ),\r
- .q ( dataout[NUM_CHAN]),\r
- .usedw ( usedw[NUM_CHAN] )\r
- );\r
- \r
- assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;\r
- assign chan_fifodata = dataout[rd_select];\r
- assign chan_usedw = usedw[rd_select];\r
- assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr};\r
-\r
-endmodule\r
projects / debian / gnuradio / blobdiff