# release: pcb 20100929
-# date: Sat Jul 2 15:43:32 2011
+# date: Sat Jul 2 16:18:27 2011
# user: bdale (Bdale Garbee,KB0G)
# host: rover
PCB["TeleBT" 291339 133858]
Grid[100.000000 0 0 0]
-Cursor[0 110000 0.000000]
+Cursor[0 23858 0.000000]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[600 1000 600 500 1500 650]
Via[177300 81700 3000 2000 0 1500 "" "thermal(0S)"]
Via[146300 37100 3000 2000 0 1500 "" "thermal(0S)"]
Via[185500 73500 3000 2000 0 1500 "" ""]
-Via[156400 80900 3000 2000 0 1500 "" ""]
+Via[159100 83400 3000 2000 0 1500 "" ""]
Via[42900 104500 3000 2000 0 1500 "" ""]
Via[218100 90400 3000 2000 0 1500 "" "thermal(0S)"]
Via[165300 76200 3000 2000 0 1500 "" ""]
Element["onsolder" "sma-edge" "J8" "SMA" 148700 112400 0 0 2 10 "auto"]
(
- Pad[7000 3000 7000 13000 6000 4000 6700 "2" "2" "onsolder,square"]
- Pad[-3000 3000 -3000 13000 6000 4000 6700 "1" "1" "onsolder,square"]
- Pad[-13000 3000 -13000 13000 6000 4000 6700 "2" "2" "onsolder,square"]
+ Pad[7000 3000 7000 13000 6000 4000 6700 "2" "2" "onsolder,square,nopaste"]
+ Pad[-3000 3000 -3000 13000 6000 4000 6700 "1" "1" "onsolder,square,nopaste"]
+ Pad[-13000 3000 -13000 13000 6000 4000 6700 "2" "2" "onsolder,square,nopaste"]
)
Line[24606 133854 24606 121063 600 2000 "clearline,lock"]
Line[12795 109252 0 109252 600 2000 "clearline,lock"]
Line[3927 0 266732 0 600 2000 "clearline,lock"]
- Line[278543 24606 913398 24606 600 2000 "clearline,lock"]
+ Line[278543 24606 291339 24606 600 2000 "clearline,lock"]
Line[266732 0 266732 12795 600 2000 "clearline,lock"]
Line[0 109252 0 3937 600 2000 "clearline,lock"]
Line[148267 78386 138780 70079 1000 2000 "clearline"]
Line[165900 66100 144000 66100 1000 2000 "clearline"]
Line[131000 25900 172700 25900 1000 2000 "clearline"]
Line[225000 72500 271810 45286 1000 2000 "clearline"]
- Line[156000 80900 165300 76200 1000 2000 "clearline"]
+ Line[159100 83400 165300 76200 1000 2000 "clearline"]
Line[144000 66100 140500 62600 1000 2000 "clearline"]
Line[154000 22900 154100 22800 1000 2000 "clearline"]
Line[130800 19900 146800 19900 1000 2000 "clearline"]
Line[61200 24137 61400 24337 1000 2000 "clearline"]
Line[96324 19150 95474 18300 1000 2000 "clearline"]
Line[145729 99681 150389 99681 2000 2000 "clearline"]
- Line[155158 74113 155158 79658 1000 2000 "clearline"]
+ Line[250200 4200 259800 13800 1000 2000 "clearline"]
Line[164114 63189 196689 63189 1000 2000 "clearline"]
Line[196689 63189 206300 72800 1000 2000 "clearline"]
Line[218092 90408 218100 90400 2500 2000 "clearline"]
Line[150389 99681 150669 99961 2000 2000 "clearline"]
Line[161800 76200 168600 76200 1000 2000 "clearline"]
Line[163100 87300 164700 88900 1000 2000 "clearline"]
- Line[155158 79658 156400 80900 1000 2000 "clearline"]
- Line[156400 80900 156400 83252 1000 2000 "clearline"]
+ Line[259800 67900 250400 77300 1000 2000 "clearline"]
+ Line[259800 13800 259800 67900 1000 2000 "clearline"]
Line[45000 12500 48700 12500 1000 2000 "clearline"]
Line[98200 18200 98100 18300 1000 2000 "clearline"]
Line[142265 55315 140615 55315 1000 2000 "clearline"]
Line[81200 16400 81400 16400 1000 2000 "clearline"]
Line[81400 16400 93600 4200 1000 2000 "clearline"]
Line[93600 4200 250200 4200 1000 2000 "clearline"]
- Line[250200 4200 259800 13800 1000 2000 "clearline"]
- Line[259800 13800 259800 67900 1000 2000 "clearline"]
- Line[259800 67900 250400 77300 1000 2000 "clearline"]
+ Line[155158 74113 155158 82410 1000 2000 "clearline"]
+ Line[155158 82410 156200 83452 1000 2000 "clearline"]
+ Line[156200 83452 159048 83452 1000 2000 "clearline"]
+ Line[159048 83452 159100 83400 1000 2000 "clearline"]
)
Layer(3 "outline")
(