tcl/board: add ESP32-S3 config for ESP USB Bridge board

[fw/openocd] / tcl / target / zynq_7000.cfg

diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index 55156ac3894a4e0d5f0177c1bd12fd03972bbed8..0272587c1e7e6fda8ec3f2bc2910a7d14fa10ce8 100644 (file)
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Xilinx Zynq-7000 All Programmable SoC
 #
@@ -9,17 +11,40 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
     -expected-id 0x23727093 \
-    -expected-id 0x03727093
+    -expected-id 0x13722093 \
+    -expected-id 0x03727093 \
+    -expected-id 0x03736093
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
-target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
     -coreid 0 -dbgbase 0x80090000
-target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \
+target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
     -coreid 1 -dbgbase 0x80092000
 target smp ${_TARGETNAME}0 ${_TARGETNAME}1
 
-adapter_khz 1000
+adapter speed 1000
 
 ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
 ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
+
+pld device virtex2 zynq_pl.bs 1
+
+set XC7_JSHUTDOWN 0x0d
+set XC7_JPROGRAM 0x0b
+set XC7_JSTART 0x0c
+set XC7_BYPASS 0x3f
+
+proc zynqpl_program {tap} {
+       global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
+       irscan $tap $XC7_JSHUTDOWN
+       irscan $tap $XC7_JPROGRAM
+       runtest 60000
+       #JSTART prevents this from working...
+       #irscan $tap $XC7_JSTART
+       runtest 2000
+       irscan $tap $XC7_BYPASS
+       runtest 2000
+}