target/xtensa: DAP-based Xtensa config files

[fw/openocd] / tcl / target / xilinx_zynqmp.cfg

diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg
index 9be781cd8f72e9dd0caad666a55df3d46c93fed0..89337297891789f53fa3ba115e2420ad5a4141f4 100644 (file)
--- a/tcl/target/xilinx_zynqmp.cfg
+++ b/tcl/target/xilinx_zynqmp.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # target configuration for
 # Xilinx ZynqMP (UltraScale+ / A53)
@@ -74,7 +76,7 @@ set _cores 4
 for { set _core 0 } { $_core < $_cores } { incr _core } {
 
     cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
-        -ctibase [lindex $CTIBASE $_core]
+        -baseaddr [lindex $CTIBASE $_core]
 
     set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
         -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
@@ -92,12 +94,14 @@ for { set _core 0 } { $_core < $_cores } { incr _core } {
     eval $_command
 }
 
+target create uscale.axi mem_ap -dap uscale.dap -ap-num 0
+
 eval $_smp_command
 targets $_TARGETNAME.0
 
 proc core_up { args } {
     global _TARGETNAME
-    foreach { core } [set args] {
+    foreach core $args {
         $_TARGETNAME.$core arp_examine
     }
 }