tcl/target: add SPDX tag

[fw/openocd] / tcl / target / ti_tms570.cfg

diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index 21da6c017a0a8f32e9eb7cf9b261a457ecce1b6a..213fb094b94c3fa37a44e77fff7d7fa53a2327fa 100644 (file)
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -1,4 +1,6 @@
-adapter_khz 1500
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed 1500
 
 if { [info exists CHIPNAME] } {
        set _CHIPNAME $CHIPNAME
@@ -20,8 +22,8 @@ source [find target/icepick.cfg]
 if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # ICEpick-C (JTAG route controller)
 # JRC_TAPID should be set before source-ing this file
@@ -50,21 +52,18 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
        -expected-id $_JRC_TAPID8 \
        -expected-id $_JRC_TAPID9 \
        -ignore-version
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
 
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
 # Cortex-R4 target
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
-       -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
+       -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
 
 # TMS570 uses quirky BE-32 mode
-$_TARGETNAME dap ti_be_32_quirks 1
-
-$_TARGETNAME configure -event gdb-attach {
-       cortex_r4 dbginit
-       halt
-}
+$_CHIPNAME.dap ti_be_32_quirks 1
 
 $_TARGETNAME configure -event "reset-assert" {
        global _CHIPNAME