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tcl/target/ti_k3: Add a gdb-attach event hook for armv8 and simplify startup function
[fw/openocd] / tcl / target / ti_k3.cfg
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index e397d2255cae037cfdc5a1d708d29dfbcbd7cb00..f2267ca12979969e941fb0d03ac8b852b039ae15 100644 (file)
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -42,6 +42,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
 #              (0)MCU 0   (1)MCU 1   (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
 
 # Finally an General Purpose(GP) MCU
 set CM4_CTIBASE                {0x20001000}
@@ -63,12 +64,7 @@ switch $_soc {
 
                # AM654 has 1 cluster of 2 R5s cores.
                set _r5_cores 2
-               set _mcu_r5_cores 2
-               set _mcu_base_core_id 0
-               set _main0_r5_cores 0
-               set _main0_base_core_id 0
-               set _main1_r5_cores 0
-               set _main1_base_core_id 0
+               set R5_NAMES {mcu_r5.0 mcu_r5.1}
 
                # Sysctrl power-ap unlock offsets
                set _sysctrl_ap_unlock_offsets {0xf0 0x50}
@@ -85,12 +81,7 @@ switch $_soc {
 
                # AM642 has 2 cluster of 2 R5s cores.
                set _r5_cores 4
-               set _mcu_r5_cores 0
-               set _mcu_base_core_id 0
-               set _main0_r5_cores 2
-               set _main0_base_core_id 0
-               set _main1_r5_cores 2
-               set _main1_base_core_id 2
+               set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
                set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
                set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
 
@@ -106,12 +97,6 @@ switch $_soc {
 
                # J721E has 3 clusters of 2 R5 cores each.
                set _r5_cores 6
-               set _mcu_r5_cores 2
-               set _mcu_base_core_id 0
-               set _main0_r5_cores 2
-               set _main0_base_core_id 2
-               set _main1_r5_cores 2
-               set _main1_base_core_id 4
        }
        j7200 {
                set _CHIPNAME j7200
@@ -123,12 +108,6 @@ switch $_soc {
 
                # J7200 has 2 clusters of 2 R5 cores each.
                set _r5_cores 4
-               set _mcu_r5_cores 2
-               set _mcu_base_core_id 0
-               set _main0_r5_cores 2
-               set _main0_base_core_id 2
-               set _main1_r5_cores 0
-               set _main1_base_core_id 0
                set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
                set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
 
@@ -167,6 +146,24 @@ $_TARGETNAME.sysctrl configure -event gdb-attach {
        halt 1000
 }
 
+proc _cpu_no_smp_up {} {
+       set _current_target [target current]
+       set _current_type [$_current_target cget -type]
+
+       $_current_target arp_examine
+       $_current_target $_current_type dbginit
+}
+
+proc _armv8_smp_up {} {
+       for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
+       }
+       # Set Default target as core 0
+       targets $::_TARGETNAME.$::_armv8_cpu_name.0
+}
+
 set _v8_smp_targets ""
 
 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -178,6 +175,20 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
                -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
 
        set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
+
+       if { $_v8_smp_debug == 0 } {
+               $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+                       _cpu_no_smp_up
+                       # gdb-attach default rule
+                       halt 1000
+               }
+       } else {
+               $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+                       _armv8_smp_up
+                       # gdb-attach default rule
+                       halt 1000
+               }
+       }
 }
 
 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
@@ -187,62 +198,39 @@ set _armv8_smp_cmd "$_armv8_cpu_name"_smp
 
 if { $_v8_smp_debug == 0 } {
        proc $_armv8_up_cmd { args } {
-               foreach { _core } [set args] {
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+               foreach _core $args {
+                       targets $_core
+                       _cpu_no_smp_up
                }
        }
 } else {
        proc $_armv8_smp_cmd { args } {
-               for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
-               }
-               # Set Default target are core 0
-               targets $::_TARGETNAME.$::_armv8_cpu_name.0
+               _armv8_smp_up
        }
-
        # Declare SMP
        target smp $:::_v8_smp_targets
 }
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
-       cti create $_CTINAME.r5.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+       set _r5_name [lindex $R5_NAMES $_core]
+       cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
                -baseaddr [lindex $R5_CTIBASE $_core]
 
        # inactive core examination will fail - wait till startup of additional core
-       target create $_TARGETNAME.r5.$_core cortex_r4 -dap $_CHIPNAME.dap \
+       target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
                -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
-}
-
-if { $_mcu_r5_cores != 0 } {
-       proc mcu_r5_up { args } {
-               foreach { _core } [set args] {
-                       set _core [expr {$_core + $::_mcu_base_core_id}]
-                       $::_TARGETNAME.r5.$_core arp_examine
-                       $::_TARGETNAME.r5.$_core cortex_r4 dbginit
-               }
-       }
-}
 
-if { $_main0_r5_cores != 0 } {
-       proc main0_r5_up { args } {
-               foreach { _core } [set args] {
-                       set _core [expr {$_core + $::_main0_base_core_id}]
-                       $::_TARGETNAME.r5.$_core arp_examine
-                       $::_TARGETNAME.r5.$_core cortex_r4 dbginit
-               }
+       $_TARGETNAME.$_r5_name configure -event gdb-attach {
+               _cpu_no_smp_up
+               # gdb-attach default rule
+               halt 1000
        }
 }
 
-if { $_main1_r5_cores != 0 } {
-       proc main1_r5_up { args } {
-               foreach { _core } [set args] {
-                       set _core [expr {$_core + $::_main1_base_core_id}]
-                       $::_TARGETNAME.r5.$_core arp_examine
-                       $::_TARGETNAME.r5.$_core cortex_r4 dbginit
-               }
+proc r5_up { args } {
+       foreach  _core $args {
+               targets $_core
+               _cpu_no_smp_up
        }
 }
 
openocd with support for Altus Metrum targets