# (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
-# Finally an M4F
+# Finally an General Purpose(GP) MCU
set CM4_CTIBASE {0x20001000}
-# M4 may be present on some very few SoCs
-set _mcu_m4_cores 0
-# M4 power-ap unlock offsets
-set _m4_ap_unlock_offsets {0xf0 0x60}
+# General Purpose MCU (M4) may be present on some very few SoCs
+set _gp_mcu_cores 0
+# General Purpose MCU power-ap unlock offsets
+set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
# Set configuration overrides for each SOC
switch $_soc {
# AM654 has 1 cluster of 2 R5s cores.
set _r5_cores 2
- set _mcu_r5_cores 2
- set _mcu_base_core_id 0
- set _main0_r5_cores 0
- set _main0_base_core_id 0
- set _main1_r5_cores 0
- set _main1_base_core_id 0
+ set R5_NAMES {mcu_r5.0 mcu_r5.1}
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x50}
# AM642 has 2 cluster of 2 R5s cores.
set _r5_cores 4
- set _mcu_r5_cores 0
- set _mcu_base_core_id 0
- set _main0_r5_cores 2
- set _main0_base_core_id 0
- set _main1_r5_cores 2
- set _main1_base_core_id 2
+ set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
# M4 processor
- set _mcu_m4_cores 1
+ set _gp_mcu_cores 1
+ }
+ am625 {
+ set _CHIPNAME am625
+ set _K3_DAP_TAPID 0x0bb7e02f
+
+ # AM625 has 1 clusters of 4 A53 cores.
+ set _armv8_cpu_name a53
+ set _armv8_cores 4
+ set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+ set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+ # AM625 has 1 cluster of 1 R5s core.
+ set _r5_cores 1
+ set R5_NAMES {main0_r5.0}
+ set R5_DBGBASE {0x9d410000}
+ set R5_CTIBASE {0x9d418000}
+
+ # sysctrl CTI base
+ set CM3_CTIBASE {0x20001000}
+ # Sysctrl power-ap unlock offsets
+ set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+ # M4 processor
+ set _gp_mcu_cores 1
+ set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
}
j721e {
set _CHIPNAME j721e
# J721E has 3 clusters of 2 R5 cores each.
set _r5_cores 6
- set _mcu_r5_cores 2
- set _mcu_base_core_id 0
- set _main0_r5_cores 2
- set _main0_base_core_id 2
- set _main1_r5_cores 2
- set _main1_base_core_id 4
}
j7200 {
set _CHIPNAME j7200
# J7200 has 2 clusters of 2 R5 cores each.
set _r5_cores 4
- set _mcu_r5_cores 2
- set _mcu_base_core_id 0
- set _main0_r5_cores 2
- set _main0_base_core_id 2
- set _main1_r5_cores 0
- set _main1_base_core_id 0
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
# M3 CTI base
set CM3_CTIBASE {0x20001000}
}
+ j721s2 {
+ set _CHIPNAME j721s2
+ set _K3_DAP_TAPID 0x0bb7502f
+
+ # J721s2 has 1 cluster of 2 A72 cores.
+ set _armv8_cpu_name a72
+ set _armv8_cores 2
+
+ # J721s2 has 3 clusters of 2 R5 cores each.
+ set _r5_cores 6
+
+ # sysctrl CTI base
+ set CM3_CTIBASE {0x20001000}
+ # Sysctrl power-ap unlock offsets
+ set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+ # M4 processor
+ set _gp_mcu_cores 1
+ set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+ }
default {
echo "'$_soc' is invalid!"
}
halt 1000
}
+proc _cpu_no_smp_up {} {
+ set _current_target [target current]
+ set _current_type [$_current_target cget -type]
+
+ $_current_target arp_examine
+ $_current_target $_current_type dbginit
+}
+
+proc _armv8_smp_up {} {
+ for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
+ $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
+ $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+ $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
+ }
+ # Set Default target as core 0
+ targets $::_TARGETNAME.$::_armv8_cpu_name.0
+}
+
set _v8_smp_targets ""
for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
+
+ if { $_v8_smp_debug == 0 } {
+ $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+ _cpu_no_smp_up
+ # gdb-attach default rule
+ halt 1000
+ }
+ } else {
+ $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+ _armv8_smp_up
+ # gdb-attach default rule
+ halt 1000
+ }
+ }
}
# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
if { $_v8_smp_debug == 0 } {
proc $_armv8_up_cmd { args } {
- foreach { _core } [set args] {
- $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
- $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+ foreach _core $args {
+ targets $_core
+ _cpu_no_smp_up
}
}
} else {
proc $_armv8_smp_cmd { args } {
- for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
- $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
- $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
- $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
- }
- # Set Default target are core 0
- targets $::_TARGETNAME.$::_armv8_cpu_name.0
+ _armv8_smp_up
}
-
# Declare SMP
target smp $:::_v8_smp_targets
}
for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
- cti create $_CTINAME.r5.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+ set _r5_name [lindex $R5_NAMES $_core]
+ cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
-baseaddr [lindex $R5_CTIBASE $_core]
# inactive core examination will fail - wait till startup of additional core
- target create $_TARGETNAME.r5.$_core cortex_r4 -dap $_CHIPNAME.dap \
+ target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
-}
-
-if { $_mcu_r5_cores != 0 } {
- proc mcu_r5_up { args } {
- foreach { _core } [set args] {
- set _core [expr {$_core + $::_mcu_base_core_id}]
- $::_TARGETNAME.r5.$_core arp_examine
- $::_TARGETNAME.r5.$_core cortex_r4 dbginit
- }
- }
-}
-if { $_main0_r5_cores != 0 } {
- proc main0_r5_up { args } {
- foreach { _core } [set args] {
- set _core [expr {$_core + $::_main0_base_core_id}]
- $::_TARGETNAME.r5.$_core arp_examine
- $::_TARGETNAME.r5.$_core cortex_r4 dbginit
- }
+ $_TARGETNAME.$_r5_name configure -event gdb-attach {
+ _cpu_no_smp_up
+ # gdb-attach default rule
+ halt 1000
}
}
-if { $_main1_r5_cores != 0 } {
- proc main1_r5_up { args } {
- foreach { _core } [set args] {
- set _core [expr {$_core + $::_main1_base_core_id}]
- $::_TARGETNAME.r5.$_core arp_examine
- $::_TARGETNAME.r5.$_core cortex_r4 dbginit
- }
+proc r5_up { args } {
+ foreach _core $args {
+ targets $_core
+ _cpu_no_smp_up
}
}
-if { $_mcu_m4_cores != 0 } {
- cti create $_CTINAME.m4 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
- target create $_TARGETNAME.m4 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
- $_TARGETNAME.m4 configure -event reset-assert { }
+if { $_gp_mcu_cores != 0 } {
+ cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
+ target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+ $_TARGETNAME.gp_mcu configure -event reset-assert { }
- proc m4_up {} {
- # To access M4, we need to enable the JTAG access for the same.
+ proc gp_mcu_up {} {
+ # To access GP MCU, we need to enable the JTAG access for the same.
# Ensure Power-AP unlocked
- $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 0] 0x00190000
- $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 1] 0x00102098
+ $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
+ $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
- $::_TARGETNAME.m4 arp_examine
+ $::_TARGETNAME.gp_mcu arp_examine
}
- $_TARGETNAME.m4 configure -event gdb-attach {
- m4_up
+ $_TARGETNAME.gp_mcu configure -event gdb-attach {
+ gp_mcu_up
# gdb-attach default rule
halt 1000
}