Add a new JTAG "setup" event; use for better DaVinci ICEpick support.

[fw/openocd] / tcl / target / ti_dm6446.cfg

diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index e96c3e15f3910c0392bbb85bf0585d04f16163ee..4dac3d5fafa43de34e35d6b51e2e3b48d0be70f7 100644 (file)
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -7,17 +7,15 @@ if { [info exists CHIPNAME] } {
    set  _CHIPNAME dm6446
 }
 
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-# Override by setting EMU01 to "-disable".
-#
-# Also note:  when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
 source [find target/icepick.cfg]
-set EMU01 "-enable"
-#set EMU01 "-disable"
 
 # Subsidiary TAP: unknown ... must enable via ICEpick
 jtag newtap $_CHIPNAME unknown -irlen 8 -disable
@@ -57,6 +55,10 @@ if { [info exists JRC_TAPID ] } {
 }
 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
 
+jtag configure $_CHIPNAME.jrc -event setup \
+       "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
 # GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
 # and the ETB memory (4K) are other options, while trace is unused.
 # Little-endian; use the OpenOCD default.