-#\r
-# Texas Instruments DaVinci family: TMS320DM365\r
-#\r
-if { [info exists CHIPNAME] } {\r
- set _CHIPNAME $CHIPNAME\r
-} else {\r
- set _CHIPNAME dm365\r
-}\r
-\r
-#\r
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB\r
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.\r
-#\r
-# Also note: when running without RTCK before the PLLs are set up, you\r
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).\r
-#\r
-source [find target/icepick.cfg]\r
-set EMU01 "-enable"\r
-#set EMU01 "-disable"\r
-\r
-# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer\r
-if { [info exists ETB_TAPID ] } {\r
- set _ETB_TAPID $ETB_TAPID\r
-} else {\r
- set _ETB_TAPID 0x2b900f0f\r
-}\r
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \\r
- -expected-id $_ETB_TAPID $EMU01\r
-jtag configure $_CHIPNAME.etb -event tap-enable \\r
- "icepick_c_tapenable $_CHIPNAME.jrc 1"\r
-\r
-# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.\r
-if { [info exists CPU_TAPID ] } {\r
- set _CPU_TAPID $CPU_TAPID\r
-} else {\r
- set _CPU_TAPID 0x0792602f\r
-}\r
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \\r
- -expected-id $_CPU_TAPID $EMU01\r
-jtag configure $_CHIPNAME.arm -event tap-enable \\r
- "icepick_c_tapenable $_CHIPNAME.jrc 0"\r
-\r
-# Primary TAP: ICEpick (JTAG route controller) and boundary scan\r
-if { [info exists JRC_TAPID ] } {\r
- set _JRC_TAPID $JRC_TAPID\r
-} else {\r
- set _JRC_TAPID 0x0b83e02f\r
-}\r
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \\r
- -expected-id $_JRC_TAPID\r
-\r
-################\r
-\r
-# various symbol definitions, to avoid hard-wiring addresses\r
-# and enable some sharing of DaVinci-family utility code\r
-global dm365\r
-set dm365 [ dict create ]\r
-\r
-# Physical addresses for controllers and memory\r
-# (Some of these are valid for many DaVinci family chips)\r
-dict set dm365 sram0 0x00010000\r
-dict set dm365 sram1 0x00014000\r
-dict set dm365 sysbase 0x01c40000\r
-dict set dm365 pllc1 0x01c40800\r
-dict set dm365 pllc2 0x01c40c00\r
-dict set dm365 psc 0x01c41000\r
-dict set dm365 gpio 0x01c67000\r
-dict set dm365 a_emif 0x01d10000\r
-dict set dm365 a_emif_cs0 0x02000000\r
-dict set dm365 a_emif_cs1 0x04000000\r
-dict set dm365 ddr_emif 0x20000000\r
-dict set dm365 ddr 0x80000000\r
-\r
-source [find target/davinci.cfg]\r
-\r
-################\r
-# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)\r
-# and the ETB memory (4K) are other options, while trace is unused.\r
-set _TARGETNAME $_CHIPNAME.arm\r
-\r
-target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME\r
-\r
-# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,\r
-# and that the work area is used only with a kernel mmu context ...\r
-$_TARGETNAME configure \\r
- -work-area-virt [expr 0xfffe0000 + 0x4000] \\r
- -work-area-phys [dict get $dm365 sram1] \\r
- -work-area-size 0x4000 \\r
- -work-area-backup 0\r
-\r
-arm7_9 dbgrq enable\r
-arm7_9 fast_memory_access enable\r
-arm7_9 dcc_downloads enable\r
-\r
-# trace setup\r
-etm config $_TARGETNAME 16 normal full etb\r
-etb config $_TARGETNAME $_CHIPNAME.etb\r
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments DaVinci family: TMS320DM365
+#
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME dm365
+}
+
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+ set _ETB_TAPID $ETB_TAPID
+} else {
+ set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 1"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+ set _CPU_TAPID $CPU_TAPID
+} else {
+ set _CPU_TAPID 0x0792602f
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+ set _JRC_TAPID $JRC_TAPID
+} else {
+ set _JRC_TAPID 0x0b83e02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+ "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
+
+# various symbol definitions, to avoid hard-wiring addresses
+# and enable some sharing of DaVinci-family utility code
+global dm365
+set dm365 [ dict create ]
+
+# Physical addresses for controllers and memory
+# (Some of these are valid for many DaVinci family chips)
+dict set dm365 sram0 0x00010000
+dict set dm365 sram1 0x00014000
+dict set dm365 sysbase 0x01c40000
+dict set dm365 pllc1 0x01c40800
+dict set dm365 pllc2 0x01c40c00
+dict set dm365 psc 0x01c41000
+dict set dm365 gpio 0x01c67000
+dict set dm365 a_emif 0x01d10000
+dict set dm365 a_emif_cs0 0x02000000
+dict set dm365 a_emif_cs1 0x04000000
+dict set dm365 ddr_emif 0x20000000
+dict set dm365 ddr 0x80000000
+
+source [find target/davinci.cfg]
+
+################
+# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
+# and the ETB memory (4K) are other options, while trace is unused.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+
+# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
+# and that the work area is used only with a kernel mmu context ...
+$_TARGETNAME configure \
+ -work-area-virt [expr {0xfffe0000 + 0x4000}] \
+ -work-area-phys [dict get $dm365 sram1] \
+ -work-area-size 0x4000 \
+ -work-area-backup 0
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it. OK to speed up after clock setup.
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
projects / fw / openocd / blobdiff