Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface

[fw/openocd] / tcl / target / ti_dm365.cfg

diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index e2d29bd5aa463977a7516da4c2b0bc4bb3b934a8..8b52746bd12ea2e887541ea113d6774ab347d990 100644 (file)
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -1,10 +1,10 @@
 #
-# Texas Instruments DaVinci family:  TMS320DM365
+# Texas Instruments DaVinci family: TMS320DM365
 #
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME dm365
+   set _CHIPNAME dm365
 }
 
 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
@@ -18,7 +18,7 @@ set EMU01 "-disable"
 source [find target/icepick.cfg]
 
 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID ] } {
+if { [info exists ETB_TAPID] } {
    set _ETB_TAPID $ETB_TAPID
 } else {
    set _ETB_TAPID 0x2b900f0f
@@ -28,7 +28,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \
        "icepick_c_tapenable $_CHIPNAME.jrc 1"
 
 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID ] } {
+if { [info exists CPU_TAPID] } {
    set _CPU_TAPID $CPU_TAPID
 } else {
    set _CPU_TAPID 0x0792602f
@@ -38,7 +38,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \
        "icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
    set _JRC_TAPID $JRC_TAPID
 } else {
    set _JRC_TAPID 0x0b83e02f
@@ -73,7 +73,7 @@ dict set dm365 ddr            0x80000000
 source [find target/davinci.cfg]
 
 ################
-# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
 # and the ETB memory (4K) are other options, while trace is unused.
 set _TARGETNAME $_CHIPNAME.arm
 
@@ -90,8 +90,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable