SMDK6410 is not target, move file to board

[fw/openocd] / tcl / target / ti_dm355.cfg

diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index da05e73435324d3288b847a079bd02547d1b0b2a..2551c3ed4c361d815fcd7a2b478f7da2fa935ae2 100644 (file)
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -6,15 +6,17 @@ if { [info exists CHIPNAME] } {
 } else {
    set  _CHIPNAME dm355
 }
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
 
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
 #
 # Also note:  when running without RTCK before the PLLs are set up, you
 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
@@ -26,7 +28,9 @@ if { [info exists ETB_TAPID ] } {
 } else {
    set _ETB_TAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+       "icepick_c_tapenable $_CHIPNAME.jrc 1"
 
 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
 if { [info exists CPU_TAPID ] } {
@@ -34,7 +38,9 @@ if { [info exists CPU_TAPID ] } {
 } else {
    set _CPU_TAPID 0x07926001
 }
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+       "icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
 if { [info exists JRC_TAPID ] } {
@@ -42,7 +48,10 @@ if { [info exists JRC_TAPID ] } {
 } else {
    set _JRC_TAPID 0x0b73b02f
 }
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+       "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
 
 ################
 
@@ -65,6 +74,9 @@ dict set dm355 a_emif_cs0     0x02000000
 dict set dm355 a_emif_cs1      0x04000000
 dict set dm355 ddr_emif                0x20000000
 dict set dm355 ddr             0x80000000
+dict set dm355 uart0           0x01c20000
+dict set dm355 uart1           0x01c20400
+dict set dm355 uart2           0x01e06000
 
 source [find target/davinci.cfg]
 
@@ -73,7 +85,7 @@ source [find target/davinci.cfg]
 # and the ETB memory (4K) are other options, while trace is unused.
 set _TARGETNAME $_CHIPNAME.arm
 
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
 
 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
 # and that the work area is used only with a kernel mmu context ...
@@ -83,6 +95,12 @@ $_TARGETNAME configure \
        -work-area-size 0x4000 \
        -work-area-backup 0
 
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable