Ensure that DaVinci chips can't start with a too-fast JTAG clock.

[fw/openocd] / tcl / target / ti_dm355.cfg

diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index e5ef8cd2fc1d86e9dc337225d8184fa7223b0956..abfba10972e33993124f0e124bc72f2698560021 100644 (file)
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -86,6 +86,12 @@ $_TARGETNAME configure \
        -work-area-size 0x4000 \
        -work-area-backup 0
 
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable