proc dbgmcu_enable_debug {} {
# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+ # freeze watchdog 1 and 2 on cores halted
+ catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+ catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
}
proc toggle_cpu0_dbg_claim0 {} {
}
proc detect_cpu1 {} {
- $::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
- set dual_core [expr {$cpu1_prsr(0) & 1}]
+ set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
+ set dual_core [expr {$cpu1_prsr & 1}]
if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
}
}
# FIXME: most of handler below will be removed once reset framework get merged
-$_CHIPNAME.ap1 configure -event reset-deassert-pre {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap1 configure -event reset-deassert-pre {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
$_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug;rcc_enable_traceclk}
$_CHIPNAME.cpu0 configure -event reset-deassert-pre {$::_CHIPNAME.cpu0 arp_examine}
$_CHIPNAME.cpu1 configure -event reset-deassert-pre {$::_CHIPNAME.cpu1 arp_examine allow-defer}