tcl/target/stm32l4x: switch to new TPIU/SWO support

[fw/openocd] / tcl / target / stm32l4x.cfg

diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index 9cad7c492c6b2ea29a905b7dfbd48f4d439324a2..dec2b2760eb7a78d3e6b8481d27eadd1ccdc1742 100644 (file)
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -15,11 +15,11 @@ if { [info exists CHIPNAME] } {
 set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
-# Smallest current target has 64kB ram, use 32kB by default to avoid surprises
+# By default use 40kB (Available RAM in smallest device STM32L412)
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x8000
+   set _WORKAREASIZE 0xa000
 }
 
 #jtag scan chain
@@ -36,18 +36,38 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
 
 if {[using_jtag]} {
    jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+} else {
+   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+      set a [llength [flash list]]
+      set _OCTOSPINAME1 $_CHIPNAME.octospi1
+      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+   }
+   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+      set b [llength [flash list]]
+      set _OCTOSPINAME2 $_CHIPNAME.octospi2
+      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400
+   }
+}
 
 # Common knowledges tells JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
@@ -55,9 +75,9 @@ flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
 #
 # Note that there is a pretty wide band where things are
 # more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -70,19 +90,50 @@ if {![using_hla]} {
    cortex_m reset_config sysresetreq
 }
 
+proc proc_post_enable {_chipname} {
+       targets $_chipname.cpu
+
+       if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+               switch [$_chipname.tpiu cget -port-width] {
+                       1 {
+                               mmw 0xE0042004 0x00000060 0x000000c0
+                               mmw 0x48001020 0x00000000 0x0000ff00
+                               mmw 0x48001000 0x000000a0 0x000000f0
+                               mmw 0x48001008 0x000000f0 0x00000000
+                         }
+                       2 {
+                               mmw 0xE0042004 0x000000a0 0x000000c0
+                               mmw 0x48001020 0x00000000 0x000fff00
+                               mmw 0x48001000 0x000002a0 0x000003f0
+                               mmw 0x48001008 0x000003f0 0x00000000
+                         }
+                       4 {
+                               mmw 0xE0042004 0x000000e0 0x000000c0
+                               mmw 0x48001020 0x00000000 0x0fffff00
+                               mmw 0x48001000 0x00002aa0 0x00003ff0
+                               mmw 0x48001008 0x00003ff0 0x00000000
+                         }
+               }
+       } else {
+               mmw 0xE0042004 0x00000020 0x000000c0
+       }
+}
+
+$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
+
 $_TARGETNAME configure -event reset-init {
        # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
        # Use MSI 24 MHz clock, compliant even with VOS == 2.
        # 3 WS compliant with VOS == 2 and 24 MHz.
        mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
-       mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10
+       mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
        # Boost JTAG frequency
-       adapter_khz 4000
+       adapter speed 4000
 }
 
 $_TARGETNAME configure -event reset-start {
        # Reset clock is MSI (4 MHz)
-       adapter_khz 500
+       adapter speed 500
 }
 
 $_TARGETNAME configure -event examine-end {
@@ -93,10 +144,3 @@ $_TARGETNAME configure -event examine-end {
        # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
        mmw 0xE0042008 0x00001800 0
 }
-
-$_TARGETNAME configure -event trace-config {
-       # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
-       # change this value accordingly to configure trace pins
-       # assignment
-       mmw 0xE0042004 0x00000020 0
-}