target/stm32h7x: add support of dual core variant of STM32H7

[fw/openocd] / tcl / target / stm32l0.cfg

diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index fd8f951bd3fc280390ec1342b1362a011a8d4b1d..e09af80018d6504d070f5bc1c1f1b019b39e3fbe 100644 (file)
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -4,6 +4,7 @@
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -14,11 +15,11 @@ if { [info exists CHIPNAME] } {
 set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
-# By default use 8kB (max ram on smallest part)
+# By default use 2kB (max ram on smallest part)
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x2000
+   set _WORKAREASIZE 0x800
 }
 
 # JTAG speed should be <= F_CPU/6.
@@ -36,9 +37,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -59,10 +61,13 @@ proc stm32l0_enable_HSI16 {} {
        echo "STM32L0: Enabling HSI16"
 
        # Set HSI16ON in RCC_CR (leave MSI enabled)
-       mww 0x40021000 0x00000101
+    mmw 0x40021000 0x00000101 0
 
        # Set HSI16 as SYSCLK (RCC_CFGR)
-       mww 0x4002100c 0x00000001
+       mmw 0x4002100c 0x00000001 0
+
+       # Wait until System clock switches to HSI16
+       while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
 
        # Increase speed
        adapter_khz 2500
@@ -75,3 +80,12 @@ $_TARGETNAME configure -event reset-init {
 $_TARGETNAME configure -event reset-start {
        adapter_khz 300
 }
+
+$_TARGETNAME configure -event examine-end {
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+       mmw 0x40015804 0x00000007 0
+
+       # Stop watchdog counters during halt
+       # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+       mmw 0x40015808 0x00001800 0
+}