+# SPDX-License-Identifier: GPL-2.0-or-later
+
#
# M0+ devices only have SW-DP, but swj-dp code works, just don't
# set any jtag related features
# JTAG speed should be <= F_CPU/6.
# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
-adapter_nsrst_delay 100
+adapter srst delay 100
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
}
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
echo "STM32L0: Enabling HSI16"
# Set HSI16ON in RCC_CR (leave MSI enabled)
- mww 0x40021000 0x00000101
+ mmw 0x40021000 0x00000101 0
# Set HSI16 as SYSCLK (RCC_CFGR)
- mww 0x4002100c 0x00000001
+ mmw 0x4002100c 0x00000001 0
+
+ # Wait until System clock switches to HSI16
+ while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
# Increase speed
- adapter_khz 2500
+ adapter speed 2500
}
$_TARGETNAME configure -event reset-init {
}
$_TARGETNAME configure -event reset-start {
- adapter_khz 300
+ adapter speed 300
}
$_TARGETNAME configure -event examine-end {