dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5
+ jtag newtap $_CHIPNAME bs -irlen 5
}
if {![using_hla]} {
# Make sure that cpu0 is selected
targets $_CHIPNAME.cpu0
+if { [info exists QUADSPI] && $QUADSPI } {
+ set a [llength [flash list]]
+ set _QSPINAME $_CHIPNAME.qspi
+ flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+} else {
+ if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+ set a [llength [flash list]]
+ set _OCTOSPINAME1 $_CHIPNAME.octospi1
+ flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+ }
+ if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+ set b [llength [flash list]]
+ set _OCTOSPINAME2 $_CHIPNAME.octospi2
+ flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
+ }
+}
+
# Clock after reset is HSI at 64 MHz, no need of PLL
adapter speed 1800
stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
# Enable debug during low power modes (uses more power)
- # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
- stm32h7x_dbgmcu_mmw 0x004 0x000001BF 0
+ # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
+ stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
+ # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
+ stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
# Stop watchdog counters during halt
# DBGMCU_APB3FZ1 |= WWDG1
adapter speed 4000
}
+# get _CHIPNAME from current target
+proc stm32h7x_get_chipname {} {
+ set t [target current]
+ set sep [string last "." $t]
+ if {$sep == -1} {
+ return $t
+ }
+ return [string range $t 0 [expr $sep - 1]]
+}
+
if {[set $_CHIPNAME.DUAL_CORE]} {
$_CHIPNAME.cpu1 configure -event examine-end {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
global $_CHIPNAME.USE_CTI
# Stop watchdog counters during halt
proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
if {![using_hla]} {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
set used_target $_CHIPNAME.ap2
set reg_addr [expr 0xE00E1000 + $reg_offset]
} {
if {[set $_CHIPNAME.USE_CTI]} {
# create CTI instances for both cores
- cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000
- cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000
+ cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
+ cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
proc stm32h7x_cti_start {} {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
# Configure Cores' CTIs to halt each other
# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
}
proc stm32h7x_cti_stop {} {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
$_CHIPNAME.cti0 enable off
$_CHIPNAME.cti1 enable off
}
proc stm32h7x_cti_prepare_restart {cti} {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
# Acknowlodge EDBGRQ at TRIGOUT0
$_CHIPNAME.$cti write INACK 0x01