+# SPDX-License-Identifier: GPL-2.0-or-later
+
# script for stm32h7x family
#
# STM32H7 provides an APB-AP at access port 2, which allows the access to
# the debug and trace features on the system APB System Debug Bus (APB-D).
target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+ swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
+ tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
}
target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
# Make sure that cpu0 is selected
targets $_CHIPNAME.cpu0
+if { [info exists QUADSPI] && $QUADSPI } {
+ set a [llength [flash list]]
+ set _QSPINAME $_CHIPNAME.qspi
+ flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+} else {
+ if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+ set a [llength [flash list]]
+ set _OCTOSPINAME1 $_CHIPNAME.octospi1
+ flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+ }
+ if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+ set b [llength [flash list]]
+ set _OCTOSPINAME2 $_CHIPNAME.octospi2
+ flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
+ }
+}
+
# Clock after reset is HSI at 64 MHz, no need of PLL
adapter speed 1800
# usage does not work with HLA, so is not done by default. That change could be
# made in a local configuration file if connect_assert_srst mode is needed for
# a specific application and a non-HLA adapter is in use.
-reset_config srst_only srst_nogate
+reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
-}
-$_CHIPNAME.cpu0 configure -event trace-config {
- # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
+ # Enable clock for tracing
+ # DBGMCU_CR |= TRACECLKEN
stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
+
+ # RM0399 (id 0x450) M7+M4 with SWO Funnel
+ # RM0433 (id 0x450) M7 with SWO Funnel
+ # RM0455 (id 0x480) M7 without SWO Funnel
+ # RM0468 (id 0x483) M7 without SWO Funnel
+ # Enable CM7 and CM4 slave ports in SWO trace Funnel
+ # Works ok also on devices single core and without SWO funnel
+ # Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
+ # SWTF_CTRL |= ENS0 | ENS1
+ stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
}
$_CHIPNAME.cpu0 configure -event reset-init {
adapter speed 4000
}
+# get _CHIPNAME from current target
+proc stm32h7x_get_chipname {} {
+ set t [target current]
+ set sep [string last "." $t]
+ if {$sep == -1} {
+ return $t
+ }
+ return [string range $t 0 [expr {$sep - 1}]]
+}
+
if {[set $_CHIPNAME.DUAL_CORE]} {
$_CHIPNAME.cpu1 configure -event examine-end {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
global $_CHIPNAME.USE_CTI
# Stop watchdog counters during halt
# like mrw, but with target selection
proc stm32h7x_mrw {used_target reg} {
- set value ""
- $used_target mem2array value 32 $reg 1
- return $value(0)
+ return [$used_target read_memory $reg 32 1]
}
# like mmw, but with target selection
proc stm32h7x_mmw {used_target reg setbits clearbits} {
set old [stm32h7x_mrw $used_target $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
+ set new [expr {($old & ~$clearbits) | $setbits}]
$used_target mww $reg $new
}
proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
if {![using_hla]} {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
set used_target $_CHIPNAME.ap2
- set reg_addr [expr 0xE00E1000 + $reg_offset]
+ set reg_addr [expr {0xE00E1000 + $reg_offset}]
} {
set used_target [target current]
- set reg_addr [expr 0x5C001000 + $reg_offset]
+ set reg_addr [expr {0x5C001000 + $reg_offset}]
}
stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
if {[set $_CHIPNAME.USE_CTI]} {
# create CTI instances for both cores
- cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000
- cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000
+ cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
+ cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
proc stm32h7x_cti_start {} {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
# Configure Cores' CTIs to halt each other
# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
}
proc stm32h7x_cti_stop {} {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
$_CHIPNAME.cti0 enable off
$_CHIPNAME.cti1 enable off
}
proc stm32h7x_cti_prepare_restart {cti} {
- # get _CHIPNAME from the current target
- set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+ set _CHIPNAME [stm32h7x_get_chipname]
# Acknowlodge EDBGRQ at TRIGOUT0
$_CHIPNAME.$cti write INACK 0x01
projects / fw / openocd / blobdiff