tcl/target: start using the new TPIU/SWO support

[fw/openocd] / tcl / target / stm32h7x.cfg

diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 8258e50312784bc49756e8c1633afc204fa5644e..26d0d9301a4f912f85af7fe4fb9d2c93ae420e0c 100644 (file)
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -77,6 +77,8 @@ if {![using_hla]} {
        # STM32H7 provides an APB-AP at access port 2, which allows the access to
        # the debug and trace features on the system APB System Debug Bus (APB-D).
        target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+       swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
+       tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
 }
 
 target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
@@ -178,13 +180,20 @@ $_CHIPNAME.cpu0 configure -event examine-end {
        stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
        # DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
        stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
-}
 
-$_CHIPNAME.cpu0 configure -event trace-config {
-       # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
-       # change this value accordingly to configure trace pins
-       # assignment
+       # Enable clock for tracing
+       # DBGMCU_CR |= TRACECLKEN
        stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
+
+       # RM0399 (id 0x450) M7+M4 with SWO Funnel
+       # RM0433 (id 0x450) M7 with SWO Funnel
+       # RM0455 (id 0x480) M7 without SWO Funnel
+       # RM0468 (id 0x483) M7 without SWO Funnel
+       # Enable CM7 and CM4 slave ports in SWO trace Funnel
+       # Works ok also on devices single core and without SWO funnel
+       # Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
+       # SWTF_CTRL |= ENS0 | ENS1
+       stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
 }
 
 $_CHIPNAME.cpu0 configure -event reset-init {