target/imx6ul: Initial support

[fw/openocd] / tcl / target / stm32h7x.cfg

diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 10477a5a70dd3da17d050b2bf606d08f5bce4074..0bfc43dfd4a7df790615a0a867291b797867cc28 100644 (file)
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -56,13 +56,31 @@ if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
-# use hardware reset, connect under reset
+# use hardware reset
+#
+# The STM32H7 does not support connect_assert_srst mode because the AXI is
+# unavailable while SRST is asserted, and that is used to access the DBGMCU
+# component at 0x5C001000 in the examine-end event handler.
+#
+# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
+# of the default AP0, and that works with SRST asserted; however, nonzero AP
+# usage does not work with HLA, so is not done by default. That change could be
+# made in a local configuration file if connect_assert_srst mode is needed for
+# a specific application and a non-HLA adapter is in use.
 reset_config srst_only srst_nogate
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 }
 
 $_TARGETNAME configure -event examine-end {
@@ -92,3 +110,4 @@ $_TARGETNAME configure -event reset-init {
        # Clock after reset is HSI at 64 MHz, no need of PLL
        adapter_khz 4000
 }
+