target/imx7: Add ahb mem_ap

[fw/openocd] / tcl / target / stm32f7x.cfg

diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index e06a34594f45040ea4e72ffb85dbffc4852e90d1..927a3e8d0595793efe57e6431c1eef92eeb24c17 100755 (executable)
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -49,6 +49,11 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
+
+# Configuring the Flash via ITCM alias as virtual
+set _FLASH_ITCM_VMA itcm-flash.alias
+flash bank $_FLASH_ITCM_VMA virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
 adapter_khz 2000
@@ -58,13 +63,24 @@ if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
-# use hardware reset, connect under reset
+# Use hardware reset.
+#
+# This target is compatible with connect_assert_srst, which may be set in a
+# board file.
 reset_config srst_only srst_nogate
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 }
 
 $_TARGETNAME configure -event examine-end {
@@ -146,10 +162,3 @@ $_TARGETNAME configure -event reset-start {
        adapter_khz 2000
 }
 
-# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
-# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
-# makes the data access cacheable. This allows reading and writing data in the
-# CPU cache from the debugger, which is far more useful than going straight to
-# RAM when operating on typical variables, and is generally no worse when
-# operating on special memory locations.
-$_CHIPNAME.dap apcsw 0x08000000 0x08000000