stm32xxx.cfg: Only touch IWDG and WWDG in DBGMCU_APB1_FZ.

[fw/openocd] / tcl / target / stm32f4x.cfg

diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 7e593e626194c41b9f239642010f280dd25f04e6..9aadf627ac0ed234fb2943a39e1ddf7d7b702628 100644 (file)
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -4,6 +4,7 @@
 # stm32 devices support both JTAG and SWD transports.
 #
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -11,11 +12,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f4x
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 64kB
@@ -49,11 +46,20 @@ if { [info exists BSTAPID] } {
   set _BSTAPID1 0x06413041
   # STM32F42xxx and STM32F43xxx
   set _BSTAPID2 0x06419041
+  # See STM Document RM0368 (Rev. 3)
+  # STM32F401B/C
+  set _BSTAPID3 0x06423041
+  # STM32F401D/E
+  set _BSTAPID4 0x06433041
+  # See STM Document RM0383 (Rev 2)
+  # STM32F411
+  set _BSTAPID5 0x06431041
 }
 
 if {[using_jtag]} {
  swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
-       -expected-id $_BSTAPID2
+     -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+     -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -64,21 +70,39 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
 #
 # Since we may be running of an RC oscilator, we crank down the speed a
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter_khz 2000
 
 adapter_nsrst_delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
 }
+
+$_TARGETNAME configure -event examine-end {
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+       mmw 0xE0042004 0x00000007 0
+
+       # Stop watchdog counters during halt
+       # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+       mmw 0xE0042008 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+       # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+       # change this value accordingly to configure trace pins
+       # assignment
+       mmw 0xE0042004 0x00000020 0
+}