tcl/target: add SPDX tag

[fw/openocd] / tcl / target / stm32f4x.cfg

diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 7e593e626194c41b9f239642010f280dd25f04e6..5be0cf505b2952e17617496b5a5dd0b40d150f45 100644 (file)
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -1,9 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32f4x family
 
 #
-# stm32 devices support both JTAG and SWD transports.
+# stm32f4 devices support both JTAG and SWD transports.
 #
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -11,18 +14,14 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f4x
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
-# By default use 64kB
+# By default use 32kB (Available RAM in smallest device STM32F410)
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x10000
+   set _WORKAREASIZE 0x8000
 }
 
 #jtag scan chain
@@ -39,46 +38,106 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
-if { [info exists BSTAPID] } {
-   set _BSTAPID $BSTAPID
-} else {
-  # See STM Document RM0090
-  # Section 38.6.2
-  # STM32F405xx/07xx and STM32F415xx/17xx
-  set _BSTAPID1 0x06413041
-  # STM32F42xxx and STM32F43xxx
-  set _BSTAPID2 0x06419041
-}
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
 
 if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
-       -expected-id $_BSTAPID2
+   jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
 #
 # Since we may be running of an RC oscilator, we crank down the speed a
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
 }
+
+$_TARGETNAME configure -event examine-end {
+       # Enable debug during low power modes (uses more power)
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+       mmw 0xE0042004 0x00000007 0
+
+       # Stop watchdog counters during halt
+       # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+       mmw 0xE0042008 0x00001800 0
+}
+
+proc proc_post_enable {_chipname} {
+       targets $_chipname.cpu
+
+       if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+               switch [$_chipname.tpiu cget -port-width] {
+                       1 {
+                               mmw 0xE0042004 0x00000060 0x000000c0
+                               mmw 0x40021020 0x00000000 0x0000ff00
+                               mmw 0x40021000 0x000000a0 0x000000f0
+                               mmw 0x40021008 0x000000f0 0x00000000
+                         }
+                       2 {
+                               mmw 0xE0042004 0x000000a0 0x000000c0
+                               mmw 0x40021020 0x00000000 0x000fff00
+                               mmw 0x40021000 0x000002a0 0x000003f0
+                               mmw 0x40021008 0x000003f0 0x00000000
+                         }
+                       4 {
+                               mmw 0xE0042004 0x000000e0 0x000000c0
+                               mmw 0x40021020 0x00000000 0x0fffff00
+                               mmw 0x40021000 0x00002aa0 0x00003ff0
+                               mmw 0x40021008 0x00003ff0 0x00000000
+                         }
+               }
+       } else {
+               mmw 0xE0042004 0x00000020 0x000000c0
+       }
+}
+
+$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
+
+$_TARGETNAME configure -event reset-init {
+       # Configure PLL to boost clock to HSI x 4 (64 MHz)
+       mww 0x40023804 0x08012008   ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
+       mww 0x40023C00 0x00000102   ;# FLASH_ACR = PRFTBE | 2(Latency)
+       mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
+       sleep 10                    ;# Wait for PLL to lock
+       mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
+       mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
+
+       # Boost JTAG frequency
+       adapter speed 8000
+}
+
+$_TARGETNAME configure -event reset-start {
+       # Reduce speed since CPU speed will slow down to 16MHz with the reset
+       adapter speed 2000
+}