+# SPDX-License-Identifier: GPL-2.0-or-later
+
# script for stm32f4x family
#
-# stm32 devices support both JTAG and SWD transports.
+# stm32f4 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
-
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
mmw 0xE0042008 0x00001800 0
}
-proc proc_post_enable {_chipname} {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
targets $_chipname.cpu
if { [$_chipname.tpiu cget -protocol] eq "sync" } {
switch [$_chipname.tpiu cget -port-width] {
1 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
mmw 0xE0042004 0x00000060 0x000000c0
mmw 0x40021020 0x00000000 0x0000ff00
mmw 0x40021000 0x000000a0 0x000000f0
mmw 0x40021008 0x000000f0 0x00000000
}
2 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
mmw 0xE0042004 0x000000a0 0x000000c0
mmw 0x40021020 0x00000000 0x000fff00
mmw 0x40021000 0x000002a0 0x000003f0
mmw 0x40021008 0x000003f0 0x00000000
}
4 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
mmw 0xE0042004 0x000000e0 0x000000c0
mmw 0x40021020 0x00000000 0x0fffff00
mmw 0x40021000 0x00002aa0 0x00003ff0
}
}
} else {
+ # Set TRACE_IOEN; TRACE_MODE to async
mmw 0xE0042004 0x00000020 0x000000c0
}
}
-$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
$_TARGETNAME configure -event reset-init {
# Configure PLL to boost clock to HSI x 4 (64 MHz)