stm32xxx.cfg: Only touch IWDG and WWDG in DBGMCU_APB1_FZ.

[fw/openocd] / tcl / target / stm32f3x.cfg

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 7ddf7d0435ad4036cdcb4693c600eb2e279f6cc3..f3ea40bad029abe5eb708a5a7695e76ea70bce9e 100644 (file)
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -99,16 +99,16 @@ proc stm32f3x_default_examine_end {} {
        mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
 
        # Stop watchdog counters during halt
-       mww 0xe0042008 0x00001800 ;# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
+       mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
 }
 
 proc stm32f3x_default_reset_init {} {
        # Configure PLL to boost clock to HSI x 8 (64 MHz)
-       mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
-       mwh 0x40021002 0x0100     ;# RCC_CR[31:16] = PLLON
-       mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
-       sleep 10                  ;# Wait for PLL to lock
-       mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1]
+       mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+       mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
+       mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
+       sleep 10                    ;# Wait for PLL to lock
+       mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
        # Boost JTAG frequency
        adapter_khz 8000
@@ -118,3 +118,10 @@ proc stm32f3x_default_reset_init {} {
 $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
 $_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
 $_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
+
+$_TARGETNAME configure -event trace-config {
+       # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+       # change this value accordingly to configure trace pins
+       # assignment
+       mmw 0xe0042004 0x00000020 0
+}