tcl: target: am437x: pass coreid

[fw/openocd] / tcl / target / stm32f3x.cfg

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 318d96c656c12b370a3b95d13e4adde37a9efa2d..f3c22af7ae2a9a570f7bdd938053c6976ac9c81e 100644 (file)
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -4,6 +4,7 @@
 # stm32 devices support both JTAG and SWD transports.
 #
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -56,22 +57,20 @@ if { [info exists BSTAPID] } {
   set _BSTAPID1 0x06422041
   # STM Document RM0313 rev 3 for STM32F37x
   set _BSTAPID2 0x06432041
-  # STM Document RM0313 rev 3 for STM32F37x Chip Revision 1.0
-  set _BSTAPID3 0x06422041
   #  STM Document RM364 rev 1 for STM32F334
-  set _BSTAPID4 0x06438041
+  set _BSTAPID3 0x06438041
   #  STM Document RM316 rev 5 for STM32F303 6/8 size
   #  STM Document RM365 rev 3 for STM32F302 6/8 size
   #  STM Document RM366 rev 2 for STM32F301 6/8 size
-  set _BSTAPID5 0x06439041
+  set _BSTAPID4 0x06439041
   #  STM Document RM016 rev 5 for STM32F303 D/E size
-  set _BSTAPID6 0x06446041
+  set _BSTAPID5 0x06446041
 }
 
 if {[using_jtag]} {
  swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
- -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4 \
- -expected-id $_BSTAPID5 -expected-id $_BSTAPID6
+ -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+ -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -89,3 +88,40 @@ if {![using_hla]} {
    # perform a soft reset
    cortex_m reset_config sysresetreq
 }
+
+proc stm32f3x_default_reset_start {} {
+       # Reset clock is HSI (8 MHz)
+       adapter_khz 1000
+}
+
+proc stm32f3x_default_examine_end {} {
+       # Enable debug during low power modes (uses more power)
+       mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+
+       # Stop watchdog counters during halt
+       mww 0xe0042008 0x00001800 ;# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f3x_default_reset_init {} {
+       # Configure PLL to boost clock to HSI x 8 (64 MHz)
+       mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+       mwh 0x40021002 0x0100     ;# RCC_CR[31:16] = PLLON
+       mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
+       sleep 10                  ;# Wait for PLL to lock
+       mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1]
+
+       # Boost JTAG frequency
+       adapter_khz 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
+
+$_TARGETNAME configure -event trace-config {
+       # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+       # change this value accordingly to configure trace pins
+       # assignment
+       mmw 0xe0042004 0x00000020 0
+}