flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0xAA

[fw/openocd] / tcl / target / stm32f3x.cfg

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index ca8e6e1d8cb9db92998c15539719d7d694e5bfc5..e3f1a34ddccdd371d19752cf0d24ef6dae603951 100644 (file)
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -28,9 +28,9 @@ if { [info exists WORKAREASIZE] } {
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -49,32 +49,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID] } {
-   set _BSTAPID $BSTAPID
-} else {
-  # STM Document RM0316 rev 5 for STM32F302/303 B/C size
-  set _BSTAPID1 0x06422041
-  # STM Document RM0313 rev 3 for STM32F37x
-  set _BSTAPID2 0x06432041
-  #  STM Document RM364 rev 1 for STM32F334
-  set _BSTAPID3 0x06438041
-  #  STM Document RM316 rev 5 for STM32F303 6/8 size
-  #  STM Document RM365 rev 3 for STM32F302 6/8 size
-  #  STM Document RM366 rev 2 for STM32F301 6/8 size
-  set _BSTAPID4 0x06439041
-  #  STM Document RM016 rev 5 for STM32F303 D/E size
-  set _BSTAPID5 0x06446041
-}
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
- -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
- -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
+   jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -91,7 +73,7 @@ if {![using_hla]} {
 
 proc stm32f3x_default_reset_start {} {
        # Reset clock is HSI (8 MHz)
-       adapter_khz 1000
+       adapter speed 1000
 }
 
 proc stm32f3x_default_examine_end {} {
@@ -99,7 +81,7 @@ proc stm32f3x_default_examine_end {} {
        mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
 
        # Stop watchdog counters during halt
-       mww 0xe0042008 0x00001800 ;# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
+       mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
 }
 
 proc stm32f3x_default_reset_init {} {
@@ -111,7 +93,7 @@ proc stm32f3x_default_reset_init {} {
        mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
        # Boost JTAG frequency
-       adapter_khz 8000
+       adapter speed 8000
 }
 
 # Default hooks