# stm32 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID] } {
- set _BSTAPID $BSTAPID
-} else {
- # STM Document RM0316 rev 5 for STM32F302/303 B/C size
- set _BSTAPID1 0x06422041
- # STM Document RM0313 rev 3 for STM32F37x
- set _BSTAPID2 0x06432041
- # STM Document RM0313 rev 3 for STM32F37x Chip Revision 1.0
- set _BSTAPID3 0x06422041
- # STM Document RM364 rev 1 for STM32F334
- set _BSTAPID4 0x06438041
- # STM Document RM316 rev 5 for STM32F303 6/8 size
- # STM Document RM365 rev 3 for STM32F302 6/8 size
- # STM Document RM366 rev 2 for STM32F301 6/8 size
- set _BSTAPID5 0x06439041
- # STM Document RM016 rev 5 for STM32F303 D/E size
- set _BSTAPID6 0x06446041
-}
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
- -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4 \
- -expected-id $_BSTAPID5 -expected-id $_BSTAPID6
+ jtag newtap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# perform a soft reset
cortex_m reset_config sysresetreq
}
+
+proc stm32f3x_default_reset_start {} {
+ # Reset clock is HSI (8 MHz)
+ adapter speed 1000
+}
+
+proc stm32f3x_default_examine_end {} {
+ # Enable debug during low power modes (uses more power)
+ mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+
+ # Stop watchdog counters during halt
+ mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f3x_default_reset_init {} {
+ # Configure PLL to boost clock to HSI x 8 (64 MHz)
+ mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+ mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
+ mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
+ sleep 10 ;# Wait for PLL to lock
+ mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+ # Boost JTAG frequency
+ adapter speed 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
+
+$_TARGETNAME configure -event trace-config {
+ # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+ # change this value accordingly to configure trace pins
+ # assignment
+ mmw 0xe0042004 0x00000020 0
+}