mips: optimize write code for speed

[fw/openocd] / tcl / target / stm32f2x.cfg

diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 49b53d7e45323554747ece2e80696a585d3763c5..cfd6274e68acc2128b39cf5bed5b699f41e57810 100644 (file)
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -1,9 +1,9 @@
-# script for stm32f2xxx
+# script for stm32f2x family
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
-   set _CHIPNAME stm32f2xxx
+   set _CHIPNAME stm32f2x
 }
 
 if { [info exists ENDIAN] } {
@@ -28,7 +28,7 @@ if { [info exists WORKAREASIZE] } {
 # that there can be a pretty wide band where things are more or less stable.
 adapter_khz 1000
 
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
 jtag_ntrst_delay 100
 
 #jtag scan chain
@@ -59,3 +59,6 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq