# stm32 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
# perform a soft reset
cortex_m reset_config sysresetreq
}
+
+$_TARGETNAME configure -event examine-end {
+ # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+ # DBG_STANDBY | DBG_STOP | DBG_SLEEP
+ mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+ # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+ # change this value accordingly to configure trace pins
+ # assignment
+ mmw 0xE0042004 0x00000020 0
+}