target/stm32xx: Endian is not configurable.

[fw/openocd] / tcl / target / stm32f1x.cfg

diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 8007ff57a8ea00f39a8fe4f598e766f4089c2434..46d70b1ed6d93e8c27d31fe84b2db9427cf0a289 100644 (file)
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -1,42 +1,42 @@
-# script for stm32
+# script for stm32f1x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
 
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME stm32
+   set _CHIPNAME stm32f1x
 }
 
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
-# By default use 16kB
+# By default use 4kB (as found on some STM32F100s)
 if { [info exists WORKAREASIZE] } {
-   set  _WORKAREASIZE $WORKAREASIZE
+   set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set  _WORKAREASIZE 0x4000
+   set _WORKAREASIZE 0x1000
 }
 
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
 #jtag scan chain
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # See STM Document RM0008
-  # Section 26.6.3
-   set _CPUTAPID 0x3ba00477
+   if { [using_jtag] } {
+      # See STM Document RM0008 Section 26.6.3
+      set _CPUTAPID 0x3ba00477
+   } {
+      # this is the SW-DP tap id not the jtag tap id
+      set _CPUTAPID 0x1ba01477
+   }
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-if { [info exists BSTAPID ] } {
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
    # FIXME this never gets used to override defaults...
    set _BSTAPID $BSTAPID
 } else {
@@ -55,14 +55,22 @@ if { [info exists BSTAPID ] } {
   set _BSTAPID6 0x06418041
   # XL line devices, Rev A
   set _BSTAPID7 0x06430041
+  # VL line devices, Rev A and Z In medium-density and high-density value line devices
+  set _BSTAPID8 0x06420041
+  # VL line devices, Rev A
+  set _BSTAPID9 0x06428041
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
        -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
        -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
-       -expected-id $_BSTAPID6 -expected-id $_BSTAPID7
+       -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \
+       -expected-id $_BSTAPID8 -expected-id $_BSTAPID9
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -70,6 +78,16 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m3 reset_config sysresetreq
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}