tcl/target: add SPDX tag

[fw/openocd] / tcl / target / stm32f0x.cfg

diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
index 104dcb9cf0e81f666de25543b27fdc31e2a169a6..5b8954eb214c6a2274c4885b8edc68b95fc71bdd 100644 (file)
--- a/tcl/target/stm32f0x.cfg
+++ b/tcl/target/stm32f0x.cfg
@@ -1,9 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32f0x family
 
 #
 # stm32 devices support SWD transports only.
 #
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -11,11 +14,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f0x
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 4kB
@@ -25,6 +24,14 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x1000
 }
 
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+       set _FLASH_SIZE $FLASH_SIZE
+} else {
+       # autodetect size
+       set _FLASH_SIZE 0
+}
+
 #jtag scan chain
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
@@ -35,21 +42,56 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 # flash size will be probed
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
+
+adapter srst delay 100
 
-adapter_nsrst_delay 100
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32f0x_default_reset_start {} {
+       # Reset clock is HSI (8 MHz)
+       adapter speed 1000
+}
+
+proc stm32f0x_default_examine_end {} {
+       # Enable debug during low power modes (uses more power)
+       mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+
+       # Stop watchdog counters during halt
+       mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f0x_default_reset_init {} {
+       # Configure PLL to boost clock to HSI x 6 (48 MHz)
+       mww 0x40021004 0x00100000   ;# RCC_CFGR = PLLMUL[2]
+       mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
+       mww 0x40022000 0x00000011   ;# FLASH_ACR = PRFTBE | LATENCY[0]
+       sleep 10                    ;# Wait for PLL to lock
+       mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+       # Boost JTAG frequency
+       adapter speed 8000
+}
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m reset_config sysresetreq
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }