at91: add at91sam9g45 support

[fw/openocd] / tcl / target / stellaris.cfg

diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 4235f9106c58eb5ae8615f3718ff752779456ff0..d6314987574409f5c7e8b327e1a02cfd6411c88a 100644 (file)
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -1,5 +1,12 @@
 # TI/Luminary Stellaris LM3S chip family
 
+# Luminary chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# For now we ignore the SPI and UART options, which
+# are usable only for ISP style initial flash programming.
+
 if { [info exists CHIPNAME] } {
    set  _CHIPNAME $CHIPNAME
 } else {
@@ -18,21 +25,21 @@ if { [info exists CPUTAPID ] } {
    set _CPUTAPID 0x0ba00477
 }
 
+# SWD DAP, and JTAG TAP, take same params for now;
+# ... even though SWD ignores all except TAPID, and
+# JTAG shouldn't need anything more then irlen. (and TAPID).
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
+       -expected-id $_CPUTAPID -ignore-version
+
 if { [info exists WORKAREASIZE ] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
+   # default to 8K working area
    set _WORKAREASIZE 0x2000
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
-       -expected-id $_CPUTAPID -ignore-version
-
-# The "lm3s" variant uses a software reset rather than SRST.
-# This stops the debug registers from being cleared; it works
-# around an erratum which should be fixed in later silicon.
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu \
-       -variant lm3s
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
 
 # 8K working area at base of ram, not backed up
 #
@@ -48,7 +55,36 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # configures and enables the PLL.  Or you might need to decrease
 # this, if you're using a slower clock.
 adapter_khz 500
-$_TARGETNAME configure -event reset-start {adapter_khz 500}
+
+source [find mem_helper.tcl]
+
+$_TARGETNAME configure -event reset-start {
+       adapter_khz 500
+
+       #       
+       # When nRST is asserted on most Stellaris devices, it clears some of
+       # the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
+       # and OpenOCD depends on those TRMs.  So we won't use SRST on those
+       # chips.  (Only power-on reset should affect debug state, beyond a
+       # few specified bits; not the chip's nRST input, wired to SRST.)
+       #
+       # REVISIT current errata specs don't seem to cover this issue.
+       # Do we have more details than this email?
+       #   https://lists.berlios.de/pipermail
+       #       /openocd-development/2008-August/003065.html
+       #
+
+       set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
+       if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
+               # Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
+               cortex_m3 reset_config sysresetreq
+       } else {
+               # Tempest and newer default to using NVIC VECTRESET
+               # this does mean a reset-init event handler is required to reset
+               # any peripherals
+               cortex_m3 reset_config vectreset
+       }
+}
 
 # flash configuration ... autodetects sizes, autoprobed
 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME