flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / tcl / target / stellaris.cfg

diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 3ab5c0b97d01c3d34965914c575972d5de3a51bb..3cd91eb372f660ebf58fc52004e0892db0d3e8e5 100644 (file)
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # TI/Luminary Stellaris LM3S chip family
 
 # Some devices have errata in returning their device class.
@@ -6,7 +8,7 @@
 
 global _DEVICECLASS
 
-if { [info exists DEVICECLASS ] } {
+if { [info exists DEVICECLASS] } {
    set _DEVICECLASS $DEVICECLASS
 } else {
    set _DEVICECLASS 0xff
@@ -20,18 +22,19 @@ source [find target/swj-dp.tcl]
 # are usable only for ISP style initial flash programming.
 
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME lm3s
+   set _CHIPNAME lm3s
 }
 
 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
-# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
+# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
+# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
 # ... we'll ignore the JTAG version field, rather than list every
 # chip revision that turns up.
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x0ba00477
@@ -41,21 +44,22 @@ if { [info exists CPUTAPID ] } {
 # ... even though SWD ignores all except TAPID, and
 # JTAG shouldn't need anything more then irlen. (and TAPID).
 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
-       -expected-id $_CPUTAPID -ignore-version
+    -expected-id $_CPUTAPID -ignore-version
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
-if { [info exists WORKAREASIZE ] } {
+if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   # default to 8K working area
-   set _WORKAREASIZE 0x2000
+   # default to 2K working area
+   set _WORKAREASIZE 0x800
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 # 8K working area at base of ram, not backed up
 #
-# NOTE:  you may need or want to reconfigure the work area;
+# NOTE: you may need or want to reconfigure the work area;
 # some parts have just 6K, and you may want to use other
 # addresses (at end of mem not beginning) or back it up.
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
@@ -63,10 +67,10 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
 # LM3S parts don't support RTCK
 #
-# NOTE:  this may be increased by a reset-init handler, after it
+# NOTE: this may be increased by a reset-init handler, after it
 # configures and enables the PLL.  Or you might need to decrease
 # this, if you're using a slower clock.
-adapter_khz 500
+adapter speed 500
 
 source [find mem_helper.tcl]
 
@@ -81,7 +85,7 @@ proc reset_peripherals {family} {
        mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
 
        # RCC and RCC2 to their reset values
-       mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))]
+       mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]
        mww $SYSCTL_RCC2 0x07806810
        mww $SYSCTL_RCC 0x078e3ad1
 
@@ -119,8 +123,8 @@ proc reset_peripherals {family} {
        mww $SYSCTL_MISC 0xffffffff
 
        # Wait for any pending flash operations to complete
-       while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 }
-       while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 }
+       while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }
+       while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }
 
        # Reset the flash controller registers
        mww $FLASH_FMA 0
@@ -130,9 +134,9 @@ proc reset_peripherals {family} {
 }
 
 $_TARGETNAME configure -event reset-start {
-       adapter_khz 500
+       adapter speed 500
 
-       #       
+       #
        # When nRST is asserted on most Stellaris devices, it clears some of
        # the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
        # and OpenOCD depends on those TRMs.  So we won't use SRST on those
@@ -150,18 +154,21 @@ $_TARGETNAME configure -event reset-start {
        if {$_DEVICECLASS != 0xff} {
           set device_class $_DEVICECLASS
        } else {
-          set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
+          set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]
        }
 
        if {$device_class == 0 || $device_class == 1 ||
-               $device_class == 3 || $device_class == 5} {
-               # Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
-               cortex_m3 reset_config sysresetreq
+               $device_class == 3 || $device_class == 5 || $device_class == 0xa} {
+               if {![using_hla]} {
+                  # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
+                  cortex_m reset_config sysresetreq
+               }
        } else {
-               # Tempest and Firestorm default to using NVIC VECTRESET
-               # peripherals will need reseting manually, see proc reset_peripherals
-               cortex_m3 reset_config vectreset
-
+               if {![using_hla]} {
+                  # Tempest and Firestorm default to using NVIC VECTRESET
+                  # peripherals will need resetting manually, see proc reset_peripherals
+                  cortex_m reset_config vectreset
+               }
                # reset peripherals, based on code in
                # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
                reset_peripherals $device_class