tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

[fw/openocd] / tcl / target / snps_hsdk.cfg

diff --git a/tcl/target/snps_hsdk.cfg b/tcl/target/snps_hsdk.cfg
index 634e07adc467b06837381a602f7c02123592f312..372b406f93a50967a2ced3ffa333dfbfe203fc29 100644 (file)
--- a/tcl/target/snps_hsdk.cfg
+++ b/tcl/target/snps_hsdk.cfg
@@ -13,7 +13,7 @@
 source [find cpu/arc/hs.tcl]
 
 set _coreid 0
-set _dbgbase [expr ($_coreid << 13)]
+set _dbgbase [expr {$_coreid << 13}]
 
 # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
 # OpenOCD is concerned EM and HS are identical.
@@ -30,8 +30,8 @@ $_TARGETNAME configure -coreid $_coreid
 $_TARGETNAME configure -dbgbase $_dbgbase
 # Flush L2$.
 $_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
-set _coreid [expr $_coreid + 1]
-set _dbgbase [expr ($_coreid << 13)]
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {$_coreid << 13}]
 
 arc_hs_init_regs
 
@@ -46,8 +46,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
 $_TARGETNAME configure -coreid $_coreid
 $_TARGETNAME configure -dbgbase $_dbgbase
 $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
-set _coreid [expr $_coreid + 1]
-set _dbgbase [expr ($_coreid << 13)]
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {$_coreid << 13}]
 
 arc_hs_init_regs
 
@@ -62,8 +62,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
 $_TARGETNAME configure -coreid $_coreid
 $_TARGETNAME configure -dbgbase $_dbgbase
 $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
-set _coreid [expr $_coreid + 1]
-set _dbgbase [expr ($_coreid << 13)]
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {$_coreid << 13}]
 
 arc_hs_init_regs
 
@@ -78,8 +78,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
 $_TARGETNAME configure -coreid $_coreid
 $_TARGETNAME configure -dbgbase $_dbgbase
 $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
-set _coreid [expr $_coreid + 1]
-set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
 arc_hs_init_regs
 
 # Enable L2 cache support for core 1.