# PXA255 comes out of reset using 3.6864 MHz oscillator.
# Until the PLL kicks in, keep the JTAG clock slow enough
# that we get no errors.
-jtag_khz 300
-$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+adapter_khz 300
+$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
# reset processing that works with PXA
proc init_reset {mode} {