# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
-# This chip is now at end-of-life. Final orders have been taken.
+# This chip is now at end-of-life. Final orders have been taken.
if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
+ set _CHIPNAME $CHIPNAME
} else {
- set _CHIPNAME pxa255
+ set _CHIPNAME pxa255
}
if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
+ set _ENDIAN $ENDIAN
} else {
- set _ENDIAN little
+ set _ENDIAN little
}
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x69264013
# PXA255 comes out of reset using 3.6864 MHz oscillator.
# Until the PLL kicks in, keep the JTAG clock slow enough
# that we get no errors.
-jtag_khz 300
-$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+adapter_khz 300
+$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
# reset processing that works with PXA
proc init_reset {mode} {