# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
-# This chip is now at end-of-life. Final orders have been taken.
+# This chip is now at end-of-life. Final orders have been taken.
if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
+ set _CHIPNAME $CHIPNAME
} else {
- set _CHIPNAME pxa255
+ set _CHIPNAME pxa255
}
if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
+ set _ENDIAN $ENDIAN
} else {
- set _ENDIAN little
+ set _ENDIAN little
}
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x69264013
}
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e -irmask 0x1f -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
-debug_level 3
+target create $_TARGETNAME xscale -endian $_ENDIAN \
+ -chain-position $_CHIPNAME.cpu
+
+# PXA255 comes out of reset using 3.6864 MHz oscillator.
+# Until the PLL kicks in, keep the JTAG clock slow enough
+# that we get no errors.
+adapter_khz 300
+$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
+
+# reset processing that works with PXA
+proc init_reset {mode} {
+ # assert both resets; equivalent to power-on reset
+ jtag_reset 1 1
+
+ # drop TRST after at least 32 cycles
+ sleep 1
+ jtag_reset 0 1
+
+ # minimum 32 TCK cycles to wake up the controller
+ runtest 50
+
+ # now the TAP will be responsive; validate scanchain
+ jtag arp_init
+
+ # ... and take it out of reset
+ jtag_reset 0 0
+}
+
+proc jtag_init {} {
+ init_reset startup
+}