tcl/target: add SPDX tag

[fw/openocd] / tcl / target / pxa255.cfg

diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 386242597cefd9b3a8ae3d59a455c67170458a62..14ee13c372be8d12fd748d2c94b399353b9afc4e 100644 (file)
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
 # This chip is now at end-of-life.  Final orders have been taken.
 
@@ -28,8 +30,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
 
 # both TRST and SRST are *required* for debug
 # DCSR is often accessed with SRST active
@@ -38,11 +40,11 @@ reset_config trst_and_srst separate srst_nogate
 # reset processing that works with PXA
 proc init_reset {mode} {
        # assert both resets; equivalent to power-on reset
-       jtag_reset 1 1
+       adapter assert trst assert srst
 
        # drop TRST after at least 32 cycles
        sleep 1
-       jtag_reset 0 1
+       adapter deassert trst assert srst
 
        # minimum 32 TCK cycles to wake up the controller
        runtest 50
@@ -51,7 +53,7 @@ proc init_reset {mode} {
        jtag arp_init
 
        # ... and take it out of reset
-       jtag_reset 0 0
+       adapter deassert trst deassert srst
 }
 
 proc jtag_init {} {