+# SPDX-License-Identifier: GPL-2.0-or-later
+
# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
# This chip is now at end-of-life. Final orders have been taken.
# PXA255 comes out of reset using 3.6864 MHz oscillator.
# Until the PLL kicks in, keep the JTAG clock slow enough
# that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
# both TRST and SRST are *required* for debug
# DCSR is often accessed with SRST active
# reset processing that works with PXA
proc init_reset {mode} {
# assert both resets; equivalent to power-on reset
- jtag_reset 1 1
+ adapter assert trst assert srst
# drop TRST after at least 32 cycles
sleep 1
- jtag_reset 0 1
+ adapter deassert trst assert srst
# minimum 32 TCK cycles to wake up the controller
runtest 50
jtag arp_init
# ... and take it out of reset
- jtag_reset 0 0
+ adapter deassert trst deassert srst
}
proc jtag_init {} {