flash/stm32l4x: add support of STM32WL5x dual core

[fw/openocd] / tcl / target / psoc6.cfg

diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index d6c5a04adc5d2512fdb64ace1dd2ff61c1f13906..bf63fd5d43246d98e019798e5f52b490a370590c 100644 (file)
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -6,7 +6,7 @@
 
 source [find target/swj-dp.tcl]
 
-adapter_khz 1000
+adapter speed 1000
 
 global _CHIPNAME
 if { [info exists CHIPNAME] } {
@@ -19,6 +19,7 @@ global TARGET
 set TARGET $_CHIPNAME.cpu
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 # Is CM0 Debugging enabled ?
 global _ENABLE_CM0
@@ -81,25 +82,36 @@ proc psoc6_deassert_post { target } {
        $target arp_examine
 
        global RESET_MODE
+       global TARGET
+
        if { $RESET_MODE ne "run" } {
                $target arp_poll
                $target arp_poll
                set st [$target curstate]
+
                if { $st eq "reset" } {
                        # we assume running state follows
                        # if reset accidentally halts, waiting is useless
                        catch { $target arp_waitstate running 100 }
                        set st [$target curstate]
                }
+
                if { $st eq "running" } {
                        echo "$target: Ran after reset and before halt..."
-                       $target arp_halt
+                       if { $target eq "${TARGET}.cm0" } {
+                               # Try to cleanly reset whole system
+                               # and halt the CM0 at entry point
+                               psoc6 reset_halt
+                               $target arp_waitstate halted 100
+                       } else {
+                               $target arp_halt
+                       }
                }
        }
 }
 
 if { $_ENABLE_CM0 } {
-       target create ${TARGET}.cm0 cortex_m -chain-position $TARGET -ap-num 1 -coreid 0
+       target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
        ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
 
        flash bank main_flash_cm0               psoc6 0x10000000 0 0 0 ${TARGET}.cm0
@@ -114,7 +126,7 @@ if { $_ENABLE_CM0 } {
 }
 
 if { $_ENABLE_CM4 } {
-       target create ${TARGET}.cm4 cortex_m -chain-position $TARGET -ap-num 2 -coreid 1
+       target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
        ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
 
        flash bank main_flash_cm4               psoc6 0x10000000 0 0 0 ${TARGET}.cm4
@@ -132,3 +144,7 @@ if { $_ENABLE_CM0 } {
        # Use CM0+ by default on dual-core devices
        targets ${TARGET}.cm0
 }
+
+if {[using_jtag]} {
+       jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
+}