flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / tcl / target / pic32mx.cfg

diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index 598c905cf49e4fdde71b3f9d70e0b2ceb6217247..df68e807aeb504ab8b23b547803405df586b3928 100644 (file)
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -23,7 +25,7 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x4000
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 #jtag scan chain
@@ -42,7 +44,7 @@ target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAM
 global _PIC32MX_DATASIZE
 global _WORKAREASIZE
 set _PIC32MX_DATASIZE 0x800
-set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)]
+set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}]
 
 $_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
 $_TARGETNAME configure -event reset-init {
@@ -50,18 +52,31 @@ $_TARGETNAME configure -event reset-init {
        # from reset the pic32 cannot execute code in ram - enable ram execution
        # minimum offset from start of ram is 2k
        #
-
        global _PIC32MX_DATASIZE
        global _WORKAREASIZE
 
-       # BMXCON
-       mww 0xbf882000 0x001f0040
+       # BMXCON        set 0 wait state option by clearing BMXWSDRM bit, bit 6
+       mww 0xbf882000 0x001f0000
        # BMXDKPBA: 2k kernel data @ 0xa0000000
        mww 0xbf882010 $_PIC32MX_DATASIZE
        # BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
        mww 0xbf882020 $_WORKAREASIZE
        # BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
        mww 0xbf882030 $_WORKAREASIZE
+
+       #
+       # Set system clock to 8Mhz if the default clock configuration is set
+       #
+
+       # SYSKEY register, make sure OSCCON is locked
+       mww 0xbf80f230 0x0
+       # SYSKEY register, write unlock sequence
+       mww 0xbf80f230 0xaa996655
+       mww 0xbf80f230 0x556699aa
+       # OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
+       mww 0xbf80f004 0x07000000
+       # SYSKEY register, relock OSCCON
+       mww 0xbf80f230 0x0
 }
 
 set _FLASHNAME $_CHIPNAME.flash0