mips: optimize write code for speed

[fw/openocd] / tcl / target / pic32mx.cfg

diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index 5e64cb84dd654fbd0b73ab0be265bd7b8b4f0672..8a8eea0ebc54660873a3fe8d021b0656f3d71974 100644 (file)
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -40,7 +40,7 @@ target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAM
 #
 
 global _PIC32MX_DATASIZE
-global _PIC32MX_PROGSIZE
+global _WORKAREASIZE
 set _PIC32MX_DATASIZE 0x800
 set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)]
 
@@ -52,16 +52,30 @@ $_TARGETNAME configure -event reset-init {
        #
 
        global _PIC32MX_DATASIZE
-       global _PIC32MX_PROGSIZE
+       global _WORKAREASIZE
 
        # BMXCON
        mww 0xbf882000 0x001f0040
-       # BMXDKPBA: 2k kernel data @ 0xa0000800
+       # BMXDKPBA: 2k kernel data @ 0xa0000000
        mww 0xbf882010 $_PIC32MX_DATASIZE
-       # BMXDUDBA: 16k kernel program @ 0xa0000800
-       mww 0xbf882020 $_PIC32MX_PROGSIZE
-       # BMXDUPBA: 0k user program
-       mww 0xbf882030 $_PIC32MX_PROGSIZE
+       # BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
+       mww 0xbf882020 $_WORKAREASIZE
+       # BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
+       mww 0xbf882030 $_WORKAREASIZE
+
+       #
+       # Set system clock to 8Mhz if the default clock configuration is set
+       #
+
+       # SYSKEY register, make sure OSCCON is locked
+       mww 0xbf80f230 0x0
+       # SYSKEY register, write unlock sequence
+       mww 0xbf80f230 0xaa996655
+       mww 0xbf80f230 0x556699aa
+       # OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
+       mww 0xbf80f004 0x07000000
+       # SYSKEY register, relock OSCCON
+       mww 0xbf80f230 0x0
 }
 
 set _FLASHNAME $_CHIPNAME.flash0