flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / tcl / target / omapl138.cfg

diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index 9a10d530cb8a8ef7bed7a9798f4072fb6f0fa0b3..2d670b98a34168cda8457243d6ea6a6cb651b113 100644 (file)
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Texas Instruments DaVinci family: OMAPL138
 #
@@ -52,8 +54,8 @@ $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable