# TI OMAP3530
-# http://focus.ti.com/docs/prod/folders/print/omap3530.html
+# http://focus.ti.com/docs/prod/folders/print/omap3530.html
# Other OMAP3 chips remove DSP and/or the OpenGL support
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME omap3530
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME omap3530
}
# ICEpick-C ... used to route Cortex, DSP, and more not shown here
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
# Subsidiary TAP: CoreSight Debug Access Port (DAP)
-if { [info exists DAP_TAPID ] } {
+if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x0b6d602f
}
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b7ae02f
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
-# GDB target: Cortex-A8, using DAP
-target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
-# FIXME much of this should be in reset event handlers
-proc omap3_dbginit { } {
- reset
- sleep 500
+# SRAM: 64K at 0x4020.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
- jtag tapenable omap3530.dap
- targets
- # sleep 1000
- # dap apsel 1
- # sleep 1000
- # dap apsel 1
- # dap info 1
+###################
- # 0xd401.0000 - ETM
- # 0xd401.1000 - Cortex-A8
- # 0xd401.9000 - TPIU (traceport)
- # 0xd401.b000 - ETB
- # 0xd401.d000 - DAPCTL
+# the reset sequence is event-driven
+# and kind of finicky...
- omap3.cpu mww 0x54011FB0 0xC5ACCE55
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
- omap3.cpu mdw 0x54011314
- omap3.cpu mdw 0x54011314
- # omap3.cpu mdw 0x54011080
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
- omap3.cpu mww 0x5401d030 0x00002000
+proc omap3_dbginit {target} {
+ # General Cortex-A8 debug initialisation
+ cortex_a dbginit
+ # Enable DBGU signal for OMAP353x
+ $target mww phys 0x5401d030 0x00002000
}
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
+# OK to speed up *after* PLL and clock tree setup.
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
+# would issue. RST_DPLL3 (4) is a cold reset.
+set PRM_RSTCTRL 0x48307250
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
+
+$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"